Abstract: The bird's heads of a local oxidation process are minimized by performing a polishing or grinding step to reduce the height of the bird's head down to a plane using the oxide inhibiting mask of the local oxidation process as a polishing stop.

Abstract: The bird's heads of a local oxidation process are minimized by performing a polishing or grinding step to reduce the height of the bird's head down to a plane using the oxide inhibiting mask of the local oxidation process as a polishing stop.

Abstract: A bipolar transistor process and device wherein the transistor is fabricated within a laterally isolated device region, into which is formed a lateral intradevice isolation groove prior to formation of device/active and contact regions. The lateral intradevice isolation groove with the lateral device isolation assists in self-alignment of device regions. The lateral intradevice isolation permits the simultaneous formation through a single mask of an active region and a contact region for a different active region both on the same planar surface of a semiconductor substrate and facilitates extremely close spacing of active regions at the planar surface.

Abstract: In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector.This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation.

Abstract: In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector.This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation.