Abstract: A backplane having a switch card interface and an adapter card interface where the switch card interface has input/outputs in an arrangement that functionally mate to a networking layer system switch card and a physical layer system switch card. The adapter card interface is coupled to the switch card interface. The adapter card interface has input/outputs in an arrangement that functionally mates to a networking layer system adapter card and a physical layer system adapter card. A method that involves forming a first and second backplane according to a manufacturing process, integrating the first backplane into a networking layer system switch, and integrating the second backplane into a physical layer system switch.

Abstract: A backplane having a switch card interface and an adapter card interface where the switch card interface has input/outputs in an arrangement that functionally mate to a networking layer system switch card and a physical layer system switch card. The adapter card interface is coupled to the switch card interface. The adapter card interface has input/outputs in an arrangement that functionally mates to a networking layer system adapter card and a physical layer system adapter card. A method that involves forming a first and second backplane according to a manufacturing process, integrating the first backplane into a networking layer system switch, and integrating the second backplane into a physical layer system switch.

Abstract: A bypass means is provided for bypassing a system clock disabling signal around a conventional system clock disabling signal processing path to reduce the amount of delay between the occurrence of the disabling signal and a stopping of the system clock.

Abstract: A clock distribution system for reducing clock skew between tightly coupled central processing units in a multi-processor system. The multi-processor system includes (1) a configuration processor for generating a first configuration signal and a second configuration signal, a first clock, a second clock, (2) a first processor having a first central processing unit, (3) a second processor having a second central processing unit, (4) a first clock generator for generating a first delayed clock signal from the first or second clock in accordance with the configuration signals, and (6) a second clock generator generating a second delayed clock signal from the first or second clock in accordance with said configuration signals.

Abstract: A circuit responsive to a switching signal for dynamically changing the frequency source of a system clock. The circuit allows addition of new frequency sources without substantial changes to the circuit because its circuitry for detecting an inactive cycle period of the new frequency source is asynchronous (i.e. not clocked by the new frequency source).

Abstract: A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal and the clock control signal and generates a system clock for the system. The system clock includes a normal system clock signal and at least one early system clock signal. The basic clock is provided through a delay tap generating a normal basic clock signal and at least one early basic clock signal. In addition, a control state machine receiving the normal basic clock signal and the at least one early basic clock signal and responsive to the clock control signal is provided for starting and stopping the system clock. The clock control signal is synchronized with the earliest system clock and supplied to the clock control state machine.