Abstract: An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.

Abstract: An ultra wideband active antenna platform can be deployed globally. A plug-and-play radio unit is removably attached to an outside of the active antenna. The PAPR can be removably plugged into a docking station to provide different technology or frequency bands specific for customers in different regions without the costly replacement of the whole antenna. In addition, the heat-generating sources (power amplifiers) with heavy heatsink structures are separated from the main antenna body, so that the whole active antenna can be installed separately since the installation weight of the antenna would be reduced.

Abstract: An ultra wideband active antenna platform can be deployed globally. A plug-and-play radio unit is removably attached to an outside of the active antenna. The PAPR can be removably plugged into a docking station to provide different technology or frequency bands specific for customers in different regions without the costly replacement of the whole antenna. In addition, the heat-generating sources (power amplifiers) with heavy heatsink structures are separated from the main antenna body, so that the whole active antenna can be installed separately since the installation weight of the antenna would be reduced.

Abstract: A stacked gate-coupled N-channel field effect transistor (GCNFET) electrostatic discharge (ESD) protection circuit involves a stack of stages. Each stage has an NFET whose body is coupled to its source. A resistor is coupled between the gate and the source. A current path is provided from a supply voltage node to the gate of each NFET such that during an ESD event, a current will flow across the resistor of the stage and induce triggering. In one embodiment, an NFET stage that is isolated from the supply voltage node by and other stage has an associated capacitance structure. During the transient voltage condition of the ESD event, current flows from the supply voltage node, through the capacitance structure and to the gate, and then through the resistor, thereby initiating triggering. The GCNFET ESD protection circuit has a trigger voltage that is less than twenty percent higher than its holding voltage.

Abstract: An electrostatic discharge (ESD) protection circuit uses two N-channel field effect transistors (NFETs) to conduct ESD current from a first to a second supply node. During the ESD event, an ESD detection circuit couples the gates of both NFETs to the first supply node through separate conductive paths. In one novel aspect, an RC trigger circuit includes a capacitance that is charged through a resistance. The resistance involves a P-channel transistor whose gate is coupled to the gate of the second NFET. During a normal power-up condition, the P-channel transistor is conductive, thereby preventing the RC trigger from triggering if the supply voltage VDD were to rise rapidly. In another novel aspect, a novel level-shifting inverter drives the second NFET. The level-shifting inverter uses a pull down resistor to avoid snap-back and also isolates the gate of the second NFET from a capacitively loaded third supply node.

Abstract: A stacked gate-coupled N-channel field effect transistor (GCNFET) electrostatic discharge (ESD) protection circuit involves a stack of stages. Each stage has an NFET whose body is coupled to its source. A resistor is coupled between the gate and the source. A current path is provided from a supply voltage node to the gate of each NFET such that during an ESD event, a current will flow across the resistor of the stage and induce triggering. In one embodiment, an NFET stage that is isolated from the supply voltage node by and other stage has an associated capacitance structure. During the transient voltage condition of the ESD event, current flows from the supply voltage node, through the capacitance structure and to the gate, and then through the resistor, thereby initiating triggering. The GCNFET ESD protection circuit has a trigger voltage that is less than twenty percent higher than its holding voltage.

Abstract: An electrostatic discharge (ESD) protection circuit uses two N-channel field effect transistors (NFETs) to conduct ESD current from a first to a second supply node. During the ESD event, an ESD detection circuit couples the gates of both NFETs to the first supply node through separate conductive paths. In one novel aspect, an RC trigger circuit includes a capacitance that is charged through a resistance. The resistance involves a P-channel transistor whose gate is coupled to the gate of the second NFET. During a normal power-up condition, the P-channel transistor is conductive, thereby preventing the RC trigger from triggering if the supply voltage VDD were to rise rapidly. In another novel aspect, a novel level-shifting inverter drives the second NFET. The level-shifting inverter uses a pull down resistor to avoid snap-back and also isolates the gate of the second NFET from a capacitively loaded third supply node.

Abstract: This invention describes a means by which a communication data bus can be electrically isolated from noise generating electrical devices such as electromagnetic actuators, which are controlled by data from the bus, using a single integrated circuit package. Specifically, an all silicon optically isolated interface within the package is used to galvanic insulate the circuitry associated with the data bus interface from the circuitry operating or receiving data from devices such as motors, sensors, etc. that are connected to a noisy environment.

Abstract: According to an exemplary embodiment, an integrated circuit includes a first circuit block having a first power bus. The integrated circuit further includes a second circuit block having a second power bus, where the first power bus is isolated from the second power bus. The integrated circuit further includes a first dedicated ESD bus, where the first dedicated ESD bus provides a discharge path from the first power bus to the second power bus and from the second power bus to the first power bus. The first power bus can be coupled to the first dedicated ESD bus by a first pair to bi-directional diodes, and the second power bus can be coupled to the first dedicated ESD bus by a second pair of bi-directional diodes.

Abstract: An ESD protection circuit includes a field effect transistor device configured such that current flowing through a hot spot filament formed in a gate region must flow in a non-linear path from a drain contact to a source contact. Source diffusion areas are segmented and staggered relative to drain diffusion areas in order to provide the non-linear current path.