Patents by Inventor Eugene ZAILER

Eugene ZAILER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sub-ranging analog to digital converter
    Patent number: 11233521
    Abstract: Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 25, 2022
    Assignee: UTI Limited Partnership
    Inventors: Leo Belostotski, Eugene Zailer, Ge Wu
  • SUB-RANGING ANALOG TO DIGITAL CONVERTER
    Publication number: 20210021278
    Abstract: Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 21, 2021
    Inventors: Leo BELOSTOTSKI, Eugene ZAILER, Ge WU