Patents by Inventor Eugene Zilberman

Eugene Zilberman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9471232
    Abstract: A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: October 18, 2016
    Assignee: SanDisk IL Ltd.
    Inventors: Rami Koren, Eran Leibinger, Nimrod Wiesz, Eugen Zilberman, Ofer Tzur, Sagiv Aharonoff, Moredechai Teicher
  • Publication number: 20150153960
    Abstract: A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 4, 2015
    Inventors: Rami Koren, Eran Leibinger, Nimrod Wiesz, Eugen Zilberman, Ofer Tzur, Sagiv Aharonoff, Moredechai Teicher
  • Patent number: 8954703
    Abstract: A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: February 10, 2015
    Assignee: SanDisk IL Ltd.
    Inventors: Rami Koren, Eran Leibinger, Nimrod Wiesz, Eugen Zilberman, Ofer Tzur, Sagiv Aharonoff, Moredechai Teicher
  • Patent number: 8700840
    Abstract: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: April 15, 2014
    Assignee: Sandisk Technologies, Inc.
    Inventors: Alexander Paley, Sergey Anatolievich Gorobets, Eugene Zilberman, Alan David Bennett, Shai Traister, Andrew Tomlin, William S. Wu, Bum Suck So
  • Patent number: 8452911
    Abstract: A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a head of the data write command to a first bank in the and a tail of the data write command to a second bank, where the head of the data write command only includes data having logical block addresses preceding logical block addresses of data in the tail of the data write command. When a status of the first bank delays execution of the data write command the controller executes a second bank maintenance procedure in the second bank while the data write command directed to the first and second banks is pending. The system includes a plurality of banks, where each bank may be associated with the same or different controllers, and the one or more controllers are adapted to execute the method noted above.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: May 28, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Sergey Anatolievich Gorobets, Alan David Bennett, Charles Michael Schroter, Eugene Zilberman
  • Patent number: 8250333
    Abstract: A method and system maintains an address table for mapping logical groups to physical addresses in a memory device. The method includes receiving a request to set an entry in the address table and selecting and flushing entries in an address table cache depending on the existence of the entry in the cache and whether the cache meets a flushing threshold criteria. The flushed entries include less than the maximum capacity of the address table cache. The flushing threshold criteria includes whether the address table cache is full or if a page exceeds a threshold of changed entries. The address table and/or the address table cache may be stored in a non-volatile memory and/or a random access memory. Improved performance may result using this method and system due to the reduced number of write operations and time needed to partially flush the address table cache to the address table.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: August 21, 2012
    Assignee: Sandisk Technologies Inc.
    Inventors: Sergey Anatolievich Gorobets, Alexander Paley, Eugene Zilberman, Alan David Bennett, Shai Traister
  • Patent number: 8244960
    Abstract: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: August 14, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Alexander Paley, Sergey Anatolievich Gorobets, Eugene Zilberman, Alan David Bennett, Shai Traister, Andrew Tomlin, William S. Wu, Bum Suck So
  • Publication number: 20120191927
    Abstract: Wear leveling techniques for re-programmable non-volatile memory systems, such as a flash EEPROM system, are described. One set of techniques uses “passive” arrangements, where, when a blocks are selected for writing, blocks with relatively low experience count are selected. This can be done by ordering the list of available free blocks based on experience count, with the “coldest” blocks placed at the front of the list, or by searching the free blocks to find a block that is “cold enough”. In another, complementary set of techniques, usable for more standard wear leveling operations as well as for “passive” techniques and other applications where the experience count is needed, the experience count of a block or meta-block is maintained as a block's attribute along its address in the data management structures, such as address tables.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 26, 2012
    Inventors: Sergey Anatolievich Gorobets, Bum Suck So, Eugene Zilberman
  • Publication number: 20120084489
    Abstract: A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a head of the data write command to a first bank in the and a tail of the data write command to a second bank, where the head of the data write command only includes data having logical block addresses preceding logical block addresses of data in the tail of the data write command. When a status of the first bank delays execution of the data write command the controller executes a second bank maintenance procedure in the second bank while the data write command directed to the first and second banks is pending. The system includes a plurality of banks, where each bank may be associated with the same or different controllers, and the one or more controllers are adapted to execute the method noted above.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: Sergey Anatolievich Gorobets, Alan David Bennett, Charles Michael Schroter, Eugene Zilberman
  • Patent number: 8094500
    Abstract: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: January 10, 2012
    Assignee: Sandisk Technologies Inc.
    Inventors: Alexander Paley, Sergey Anatolievich Gorobets, Eugene Zilberman, Alan David Bennett, Shai Traister, Andrew Tomlin, William S. Wu, Bum Suck So
  • Patent number: 8040744
    Abstract: Techniques for the management of spare blocks in re-programmable non-volatile memory system, such as a flash EEPROM system, are presented. In one set of techniques, for a memory partitioned into two sections (for example a binary section and a multi-state section), where blocks of one section are more prone to error, spare blocks can be transferred from the more error prone partition to the less error prone partition. In another set of techniques for a memory partitioned into two sections, blocks which fail in the more error prone partition are transferred to serve as spare blocks in the other partition. In a complementary set of techniques, a 1-bit time stamp is maintained for free blocks to determine whether the block has been written recently. Other techniques allow for spare blocks to be managed by way of a logical to physical conversion table by assigning them logical addresses that exceed the logical address space of which a host is aware.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: October 18, 2011
    Assignee: SanDisk Technologies Inc.
    Inventors: Sergey Anatolievich Gorobets, Alan David Bennett, Eugene Zilberman
  • Patent number: 7911836
    Abstract: The present invention discloses systems and methods for restoring data in flash memory after an operational failure. The method includes: setting bits of a data buffer in accordance with the data; programming a plurality of memory cells in accordance with the data buffer; and upon failure of the programming step, restoring the data buffer to be set in accordance with the data, wherein the restoring is based only on a present state of the data buffer and on a present state of the plurality of memory cells. A memory device includes: at least one cell; and a controller operative to store data in at least one cell by steps including those described in the method above. The system includes: a memory device that includes at least one cell; and a processor operative to store data in at least one cell by steps including those described in the method above.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: March 22, 2011
    Assignee: Sandisk IL Ltd
    Inventor: Eugene Zilberman
  • Publication number: 20100174846
    Abstract: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 8, 2010
    Inventors: Alexander Paley, Sergey Anatolievich Gorobets, Eugene Zilberman, Alan David Bennett, Shai Traister, Andrew Tomlin, William S. Wu, Bum Suck So
  • Publication number: 20100172179
    Abstract: Techniques for the management of spare blocks in re-programmable non-volatile memory system, such as a flash EEPROM system, are presented. In one set of techniques, for a memory partitioned into two sections (for example a binary section and a multi-state section), where blocks of one section are more prone to error, spare blocks can be transferred from the more error prone partition to the less error prone partition. In another set of techniques for a memory partitioned into two sections, blocks which fail in the more error prone partition are transferred to serve as spare blocks in the other partition. In a complementary set of techniques, a 1-bit time stamp is maintained for free blocks to determine whether the block has been written recently. Other techniques allow for spare blocks to be managed by way of a logical to physical conversion table by assigning them logical addresses that exceed the logical address space of which a host is aware.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 8, 2010
    Inventors: Sergey Anatolievich Gorobets, Alan David Bennett, Eugene Zilberman
  • Publication number: 20100174845
    Abstract: Wear leveling techniques for re-programmable non-volatile memory systems, such as a flash EEPROM system, are described. One set of techniques uses “passive” arrangements, where, when a blocks are selected for writing, blocks with relatively low experience count are selected. This can be done by ordering the list of available free blocks based on experience count, with the “coldest” blocks placed at the front of the list, or by searching the free blocks to find a block that is “cold enough”. In another, complementary set of techniques, usable for more standard wear leveling operations as well as for “passive” techniques and other applications where the experience count is needed, the experience count of a block or meta-block is maintained as a block's attribute along its address in the data management structures, such as address tables.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 8, 2010
    Inventors: Sergey Anatolievich Gorobets, Bum Suck So, Eugene Zilberman
  • Publication number: 20100174847
    Abstract: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 8, 2010
    Inventors: Alexander Paley, Sergey Anatolievich Gorobets, Eugene Zilberman, Alan David Bennett, Shai Traister, Andrew Tomlin, William S. Wu, Bum Suck So
  • Publication number: 20100174869
    Abstract: A method and system maintains an address table for mapping logical groups to physical addresses in a memory device. The method includes receiving a request to set an entry in the address table and selecting and flushing entries in an address table cache depending on the existence of the entry in the cache and whether the cache meets a flushing threshold criteria. The flushed entries include less than the maximum capacity of the address table cache. The flushing threshold criteria includes whether the address table cache is full or if a page exceeds a threshold of changed entries. The address table and/or the address table cache may be stored in a non-volatile memory and/or a random access memory. Improved performance may result using this method and system due to the reduced number of write operations and time needed to partially flush the address table cache to the address table.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 8, 2010
    Inventors: Sergey Anatolievich Gorobets, Alexander Paley, Eugene Zilberman, Alan David Bennett, Shai Traister
  • Publication number: 20100172180
    Abstract: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 8, 2010
    Inventors: Alexander Paley, Sergey Anatolievich Gorobets, Eugene Zilberman, Alan David Bennett, Shai Traister, Andrew Tomlin, William S. Wu, Bum Suck So
  • Publication number: 20090259808
    Abstract: A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel.
    Type: Application
    Filed: June 24, 2009
    Publication date: October 15, 2009
    Applicant: SANDISK IL LTD.
    Inventors: Rami Koren, Eran Leibinger, Nimrod Wiesz, Eugen Zilberman, Ofer Tzur, Sagiv Aharonoff, Mordechai Teicher
  • Publication number: 20090094482
    Abstract: The present invention discloses systems and methods for restoring data in flash memory after an operational failure. The method includes: setting bits of a data buffer in accordance with the data; programming a plurality of memory cells in accordance with the data buffer; and upon failure of the programming step, restoring the data buffer to be set in accordance with the data, wherein the restoring is based only on a present state of the data buffer and on a present state of the plurality of memory cells. A memory device includes: at least one cell; and a controller operative to store data in at least one cell by steps including those described in the method above. The system includes: a memory device that includes at least one cell; and a processor operative to store data in at least one cell by steps including those described in the method above.
    Type: Application
    Filed: November 21, 2008
    Publication date: April 9, 2009
    Inventor: Eugene Zilberman