Patents by Inventor Eugenio Dentoni Litta
Eugenio Dentoni Litta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230197831Abstract: A method is provided for forming a semiconductor device.Type: ApplicationFiled: December 9, 2022Publication date: June 22, 2023Inventors: Boon Teik Chan, Hans Mertens, Eugenio Dentoni Litta
-
Patent number: 11545401Abstract: In one aspect, a method of forming a semiconducting device can comprise forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.Type: GrantFiled: December 8, 2020Date of Patent: January 3, 2023Assignee: IMEC vzwInventors: Boon Teik Chan, Eugenio Dentoni Litta, Liping Zhang
-
Patent number: 11515399Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure.Type: GrantFiled: December 4, 2020Date of Patent: November 29, 2022Assignee: IMEC vzwInventors: Eugenio Dentoni Litta, Juergen Boemmels, Julien Ryckaert, Naoto Horiguchi, Pieter Weckx
-
Patent number: 11488954Abstract: The disclosed technology relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to field-effect transistors operating at different voltages and methods for integrating the same.Type: GrantFiled: December 18, 2020Date of Patent: November 1, 2022Assignee: IMEC vzwInventors: Eugenio Dentoni Litta, Alessio Spessot
-
Patent number: 11462443Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer.Type: GrantFiled: December 3, 2020Date of Patent: October 4, 2022Assignee: IMEC vzwInventors: Eugenio Dentoni Litta, Juergen Boemmels, Julien Ryckaert, Naoto Horiguchi, Pieter Weckx
-
Patent number: 11367662Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having a first field-effect transistor (FET) device and a second FET device comprises forming the first and second FET devices from a first stack and a second stack comprising a channel material arranged on a sacrificial material. The method can include forming first spacers at sidewalls of the first and second stacks, and forming a second spacer between the first spacers. After recessing of the sacrificial material and removal of the first spacers, gate structures may be formed, wrapping around the at least partly released channel portions. The gate structure of the first transistor device can be separated from the gate structure of the second transistor device by the second spacer.Type: GrantFiled: July 24, 2020Date of Patent: June 21, 2022Assignee: IM EC vzwInventors: Eugenio Dentoni Litta, Yusuke Oniki, Lars-Ake Ragnarsson, Naoto Horiguchi
-
Patent number: 11348842Abstract: A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.Type: GrantFiled: October 19, 2020Date of Patent: May 31, 2022Assignee: Imec VZWInventors: Eugenio Dentoni Litta, Boon Teik Chan, Steven Demuynck
-
Patent number: 11335597Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.Type: GrantFiled: August 1, 2020Date of Patent: May 17, 2022Assignee: IMEC vzwInventors: Eugenio Dentoni Litta, Anshul Gupta, Julien Ryckaert, Boon Teik Chan
-
Publication number: 20220093734Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.Type: ApplicationFiled: September 16, 2021Publication date: March 24, 2022Inventors: Boon Teik CHAN, Hans MERTENS, Eugenio DENTONI LITTA
-
Patent number: 11164942Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second nanosheet transistor structure, each comprising a source, a drain, and a channel extending between the source and the drain in a first direction, and a gate extending across the channel, wherein the first and second nanosheet transistor structures are spaced apart in a second direction, transverse to the first direction, by an insulating wall extending in the first direction.Type: GrantFiled: May 27, 2020Date of Patent: November 2, 2021Assignee: IMEC VZWInventors: Pieter Weckx, Julien Ryckaert, Eugenio Dentoni Litta
-
Publication number: 20210202480Abstract: The disclosed technology relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to field-effect transistors operating at different voltages and methods for integrating the same.Type: ApplicationFiled: December 18, 2020Publication date: July 1, 2021Inventors: Eugenio Dentoni Litta, Alessio Spessot
-
Publication number: 20210193821Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure.Type: ApplicationFiled: December 4, 2020Publication date: June 24, 2021Inventors: Eugenio Dentoni Litta, Juergen Boemmels, Julien Ryckaert, Naoto Horiguchi, Pieter Weckx
-
Publication number: 20210183711Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer.Type: ApplicationFiled: December 3, 2020Publication date: June 17, 2021Inventors: Eugenio Dentoni Litta, Juergen Boemmels, Julien Ryckaert, Naoto Horiguchi, Pieter Weckx
-
Publication number: 20210175130Abstract: In one aspect, a method of forming a semiconducting device can comprise forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.Type: ApplicationFiled: December 8, 2020Publication date: June 10, 2021Inventors: Boon Teik Chan, Eugenio Dentoni Litta, Liping Zhang
-
Publication number: 20210118747Abstract: A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.Type: ApplicationFiled: October 19, 2020Publication date: April 22, 2021Inventors: Eugenio Dentoni Litta, Boon Teik Chan, Steven Demuynck
-
Publication number: 20210035860Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.Type: ApplicationFiled: August 1, 2020Publication date: February 4, 2021Inventors: Eugenio Dentoni Litta, Anshul Gupta, Julien Ryckaert, Boon Teik Chan
-
Publication number: 20210028068Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having a first field-effect transistor (FET) device and a second FET device comprises forming the first and second FET devices from a first stack and a second stack comprising a channel material arranged on a sacrificial material. The method can include forming first spacers at sidewalls of the first and second stacks, and forming a second spacer between the first spacers. After recessing of the sacrificial material and removal of the first spacers, gate structures may be formed, wrapping around the at least partly released channel portions. The gate structure of the first transistor device can be separated from the gate structure of the second transistor device by the second spacer.Type: ApplicationFiled: July 24, 2020Publication date: January 28, 2021Inventors: Eugenio Dentoni Litta, Yusuke Oniki, Lars-Ake Ragnarsson, Naoto Horiguchi