Patents by Inventor Euhan Chong
Euhan Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11675386Abstract: Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock signal. The method further comprises outputting, by a static phase interpolator, an edge clock signal based on the first and second center clock signals.Type: GrantFiled: August 9, 2021Date of Patent: June 13, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Euhan Chong, Mohammad Sadegh Jalali, Behzad Dehlaghi
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Publication number: 20230041998Abstract: Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock signal. The method further comprises outputting, by a static phase interpolator, an edge clock signal based on the first and second center clock signals.Type: ApplicationFiled: August 9, 2021Publication date: February 9, 2023Inventors: Euhan CHONG, Mohammad Sadegh JALALI, Behzad DEHLAGHI
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Patent number: 11431530Abstract: A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.Type: GrantFiled: September 2, 2020Date of Patent: August 30, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventor: Euhan Chong
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Patent number: 11343125Abstract: There is provided a method including receiving, by a multiplexer, input signals having a first rate, applying, by an equalizer in the multiplexer, equalization on the input signals passed through respective signal paths in the multiplexer, and outputting, by the multiplexer, an output signal comprising a selected signal of equalized versions of the input signals produced by the equalization, the output signal having a second rate greater than the first rate. There is further provided a device that includes a multiplexer and a signal driver having an input connected to the output of the equalizer. The multiplexer includes a plurality of inputs to receive respective input signals, an output to provide an output signal selected from among the input signals, and an equalizer to apply equalization on the input signals that are passed through the multiplexer, the equalization to provide the selected signals as equalized signals at the output of the multiplexer.Type: GrantFiled: July 8, 2020Date of Patent: May 24, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventor: Euhan Chong
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Publication number: 20220070029Abstract: A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.Type: ApplicationFiled: September 2, 2020Publication date: March 3, 2022Inventor: Euhan CHONG
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Publication number: 20220014399Abstract: There is provided a method including receiving, by a multiplexer, input signals having a first rate, applying, by an equalizer in the multiplexer, equalization on the input signals passed through respective signal paths in the multiplexer, and outputting, by the multiplexer, an output signal comprising a selected signal of equalized versions of the input signals produced by the equalization, the output signal having a second rate greater than the first rate. There is further provided a device that includes a multiplexer and a signal driver having an input connected to the output of the equalizer. The multiplexer includes a plurality of inputs to receive respective input signals, an output to provide an output signal selected from among the input signals, and an equalizer to apply equalization on the input signals that are passed through the multiplexer, the equalization to provide the selected signals as equalized signals at the output of the multiplexer.Type: ApplicationFiled: July 8, 2020Publication date: January 13, 2022Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventor: Euhan CHONG
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Patent number: 11069989Abstract: The disclosed systems, structures, and methods are directed to a multi-level multi-mode transmitter, employing a first pre-driver configured to receive M-parallel data streams and to convert the M-parallel data streams into a serial data stream, a first voltage-driver configured to operate on the single data stream and to provide a voltage in accordance with the single data stream, a second pre-driver configured to receive and process the M-parallel data streams in accordance with at least one of the following modes: moderate impedance (Z) post-cursor mode, moderate Z pre-cursor mode, low Z high-swing mode, low Z post-cursor mode, and low Z pre-cursor mode, and convert the processed M-parallel data streams into a first serial stream and a second serial stream and a second voltage-driver configured to operate on the first serial stream and the second serial stream and to provide a voltage.Type: GrantFiled: July 15, 2019Date of Patent: July 20, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Faisal Ahmed Musa, Euhan Chong
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Publication number: 20210021056Abstract: The disclosed systems, structures, and methods are directed to a multi-level multi-mode transmitter, employing a first pre-driver configured to receive M-parallel data streams and to convert the M-parallel data streams into a serial data stream, a first voltage-driver configured to operate on the single data stream and to provide a voltage in accordance with the single data stream, a second pre-driver configured to receive and process the M-parallel data streams in accordance with at least one of the following modes: moderate impedance (Z) post-cursor mode, moderate Z pre-cursor mode, low Z high-swing mode, low Z post-cursor mode, and low Z pre-cursor mode, and convert the processed M-parallel data streams into a first serial stream and a second serial stream and a second voltage-driver configured to operate on the first serial stream and the second serial stream and to provide a voltage.Type: ApplicationFiled: July 15, 2019Publication date: January 21, 2021Inventors: Faisal Ahmed MUSA, Euhan CHONG
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Patent number: 10880133Abstract: Devices and methods for finite impulse response (FIR) feed forward equalization (FFE) at a transmitter are provided. A voltage-mode driver circuit has a main driver and an equalization driver. The main driver drives the digital output signal based on a received digital input signal. The equalization function of the equalization driver is enabled or disabled for a short duration of time to provide at least one of FIR equalization and pre-emphasis to the digital output signal. Pre-emphasis is effected by enabling a low-resistance path of the equalization driver based on the digital input signal such that, when the low-resistance path is enabled, it reduces the transmission resistance for a short period of time.Type: GrantFiled: May 10, 2018Date of Patent: December 29, 2020Assignee: Huawei Technologies Co., Ltd.Inventor: Euhan Chong
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Patent number: 10530376Abstract: An apparatus comprises a ring oscillator comprising a plurality of delay stages connected in cascade and an injection apparatus comprising a plurality of injection devices, wherein the injection devices receive a reference clock from their inputs and outputs of the injection devices are coupled to respective outputs of the delay stages, and wherein each injection device comprises a polarity selection stage having inputs coupled to the reference clock and an adjustable gain stage having inputs coupled to outputs of the polarity selection stage and outputs coupled to outputs of a corresponding delay stage.Type: GrantFiled: December 31, 2013Date of Patent: January 7, 2020Assignee: Futurewei Technologies, Inc.Inventor: Euhan Chong
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Patent number: 10484044Abstract: Devices and methods for communicating back-channel data over a communication link are provided. The termination impedance of the communication link at the receiver and/or transmitter side may be modulated to encode back-channel data as signal reflections in the communication link. The corresponding device at the other end of the communication link may detect these reflections and decode them to recover the back-channel data.Type: GrantFiled: May 1, 2018Date of Patent: November 19, 2019Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventor: Euhan Chong
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Patent number: 10483343Abstract: A device includes a first inductor positioned on a first substrate. The first inductor has at least one turn in a plane that is perpendicular to a plane of the first substrate. The first inductor is positioned for near field coupling with a second inductor. The second inductor is positioned on a second substrate, with at least one turn that is in a plane perpendicular to a plane of the second substrate. The second inductor is substantially parallel to the first inductor. Such an arrangement may be used for near field coupling, including edge-to-edge coupling, between two integrated circuits.Type: GrantFiled: June 16, 2017Date of Patent: November 19, 2019Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Euhan Chong, Davide Tonietto, Zhonggui Xiang
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Publication number: 20190349226Abstract: Devices and methods for finite impulse response (FIR) feed forward equalization (FFE) at a transmitter are provided. A voltage-mode driver circuit has a main driver and an equalization driver. The main driver drives the digital output signal based on a received digital input signal. The equalization function of the equalization driver is enabled or disabled for a short duration of time to provide at least one of FIR equalization and pre-emphasis to the digital output signal. Pre-emphasis is effected by enabling a low-resistance path of the equalization driver based on the digital input signal such that, when the low-resistance path is enabled, it reduces the transmission resistance for a short period of time.Type: ApplicationFiled: May 10, 2018Publication date: November 14, 2019Inventor: Euhan Chong
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Publication number: 20190341963Abstract: Devices and methods for communicating back-channel data over a communication link are provided. The termination impedance of the communication link at the receiver and/or transmitter side may be modulated to encode back-channel data as signal reflections in the communication link. The corresponding device at the other end of the communication link may detect these reflections and decode them to recover the back-channel data.Type: ApplicationFiled: May 1, 2018Publication date: November 7, 2019Inventor: Euhan Chong
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Publication number: 20180366535Abstract: A device includes a first inductor positioned on a first substrate. The first inductor has at least one turn in a plane that is perpendicular to a plane of the first substrate. The first inductor is positioned for near field coupling with a second inductor. The second inductor is positioned on a second substrate, with at least one turn that is in a plane perpendicular to a plane of the second substrate. The second inductor is substantially parallel to the first inductor. Such an arrangement may be used for near field coupling, including edge-to-edge coupling, between two integrated circuits.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Inventors: Euhan Chong, Davide Tonietto, Zhonggui Xiang
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Publication number: 20180227001Abstract: A transmitter driver is disclosed. The transmitter driver includes first and second voltage mode drivers and a secondary data path. The secondary data path is connected in parallel with the first and second voltage mode drivers. A high frequency booster provides a high frequency path for boost current from the current source, to enable a high frequency voltage boost at the output ports.Type: ApplicationFiled: February 6, 2017Publication date: August 9, 2018Inventors: Euhan Chong, Yingying Fu
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Patent number: 10044377Abstract: A transmitter driver is disclosed. The transmitter driver includes first and second voltage mode drivers and a secondary data path. The secondary data path is connected in parallel with the first and second voltage mode drivers. A high frequency booster provides a high frequency path for boost current from the current source, to enable a high frequency voltage boost at the output ports.Type: GrantFiled: February 6, 2017Date of Patent: August 7, 2018Assignee: Huawei Technologies Co., Ltd.Inventors: Euhan Chong, Yingying Fu
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Publication number: 20180212634Abstract: Described herein is a termination circuit for a receiver receiving a single-ended signal. The termination circuit includes the first stage having a low-pass transfer function having a first pole/zero pair, and a second stage coupled to the first stage, where the second stage has a high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair.Type: ApplicationFiled: January 24, 2017Publication date: July 26, 2018Inventors: Euhan Chong, Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone
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Patent number: 10033419Abstract: Described herein is a termination circuit for a receiver receiving a single-ended signal. The termination circuit includes the first stage having a low-pass transfer function having a first pole/zero pair, and a second stage coupled to the first stage, where the second stage has a high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair.Type: GrantFiled: January 24, 2017Date of Patent: July 24, 2018Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Euhan Chong, Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone
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Patent number: 9871529Abstract: Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC. A timing detector circuit is coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC. The timing detector circuit outputs a timing detector signal representing an internal timing of the SAR ADC. The timing detector signal is generated based on the one or more internal signals. A regulator circuit is coupled to the timing detector circuit to receive the timing detector signal. The regulator circuit is also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC. The feedback signal is generated based on the timing detector signal to control the internal timing of the SAR ADC to match a target timing.Type: GrantFiled: February 6, 2017Date of Patent: January 16, 2018Assignee: Huawei Technologies Co., Ltd.Inventors: Euhan Chong, Semyon Lebedev, Marc-Andre LaCroix