Abstract: A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory cells and a flag memory cell. The flag memory cell is configured to be more susceptible to electrical stress on its retention of data than the normal memory cells. The memory monitors data stored in the flag memory cell to monitor a data retention characteristic of the normal memory cells.

Abstract: Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.

Abstract: Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.

Abstract: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

Abstract: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

Abstract: A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory cells and a flag memory cell. The flag memory cell is configured to be more susceptible to electrical stress on its retention of data than the normal memory cells. The memory monitors data stored in the flag memory cell to monitor a data retention characteristic of the normal memory cells.

Abstract: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

Abstract: An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns. The memory cells are erased at the same time. An erase-verify operation is performed for the erased memory cells. The erase method is repeated under different bias conditions of the rows. An erase-verify operation is successively performed twice or more under different bias conditions of wordlines to decrease cell current caused by a weak cell which may be produced in a process. Thus, a reliability of an erase-verify operation is enhance to increase a yield.

Abstract: An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns. The memory cells are erased at the same time. An erase-verify operation is performed for the erased memory cells. The erase method is repeated under different bias conditions of the rows. An erase-verify operation is successively performed twice or more under different bias conditions of wordlines to decrease cell current caused by a weak cell which may be produced in a process. Thus, a reliability of an erase-verify operation is enhance to increase a yield.

Abstract: Integrated circuit devices include a comparator circuit and a fuse programmable input circuit. The fuse programmable input circuit generates first and second differential input signals at voltage levels that can be controlled through a pair of fuses. The comparator circuit generates an output signal based on the relative voltage levels exhibited by the first and second differential input signals. In particular, the output signal is driven to a first logic state when the voltage difference between the first and second differential input signals is positive and the output signal is driven to a second logic state, which is opposite the first logic state, when the voltage difference is negative. Because the comparator is responsive to the relative difference between the voltage levels of the first and second differential input signals and not the absolute magnitudes of the voltage levels, fuse remnants that may exist after the fuse programmable input circuit has been programmed (i.e.

Abstract: A method for providing a fuse apparatus for a semiconductor device includes providing at least one fuse portion of the fuse apparatus with at least two fuses connected in series. A circuit, such as a redundancy decoder, is adapted to utilize a fuse apparatus including at least one fuse portion having a plurality of fuses connected in series. The fuse apparatus is preferably provided with polysilicon fuses which are cut using a laser beam cutting device. The fuse apparatus provides an increased probability of accurately cutting a fuse portion of a fuse means necessary to effect a proper repair of the circuit and to improve the semiconductor circuit operational reliability.