Abstract: A method for forming micro contacts of a semiconductor device, including the steps of forming a transistor on a semiconductor substrate, forming a pad conductive layer over the resulting structure, forming an insulating film over the resulting structure, thereby planarizing the structure, forming a photoresist film pattern on the planarized structure by use of a contact mask, etching the insulating film using the photoresist film pattern as a mask, thereby partially exposing the pad conductive layer, selectively over-growing the exposed portion of the pad conductive layer, thereby forming a second conductive layer, etching the insulating film using the pad conductive layer as a mask, thereby forming an insulating film pattern, fully etching both the overgrown second conductive layer and the pad conductive layer to a desired depth, filling the etched portions of the conductive layers with another insulating film, thereby planarizing the structure, and forming a bit line on a desired portion of the planarized s

Abstract: A DRAM capacitor and a method for fabricating the same, capable of achieving an increase in surface area and thereby an increase in capacitance while reducing the topology, by simply forming a conduction layer, as a charge storage electrode, comprised of conduction spacers around a double-layer pin-shaped conduction layer pattern or a combination of a central conduction layer pattern and an outer conduction layer pattern having an upwardly-opened dome structure surrounding the central conduction layer pattern, using an etch rate difference between insulating films.

Abstract: There is disclosed a method for the fabrication of capacitor, comprising the steps of: coating an insulating film over a transistor and applying planarization to the insulating film; etching the insulating film, to form a contact hole exposing an active region of the transistor therethrough and forming a conductive polysilicon film over the insulating film, so as to bring the conductive polysilicon film into contact with the active region; forming a plurality of first spacer oxide films and a plurality of second spacer oxide films on the polysilicon film, in due order; carrying out etch, so as to attenuate the conductive polysilicon films; etching the conductive polysilicon film by use of the plurality of spacer oxide films as an etch mask, to form a charge storage electrode, the charge storage electrode being determined by the attenuation of the conductive polysilicon in size; and coating the surface of the charge storage electrode with a dielectric film, and forming a plate electrode on the dielectric film.

Abstract: There are disclosed a semiconductor memory device and a method for fabrication thereof. The semiconductor memory device comprises a storage electrode connected with a source region of a MOSFET and formed with a wider area than that of the mask therefor, having a structure which is comprised of a spacer-shaped hollow cylinder of impurity-doped polysilicon containing three separate solid cylinders of impurity-doped polysilicon therein, a column filling the contact hole, and a disc-like plate, the spacer-shaped hollow cylinder and the three separate cylinders standing on the disc-like plate from which the column is extended toward the active region. It has an advantage of increasing the efficient area of a storage electrode of a semiconductor device, thereby improving the capacitance. In addition, it becomes more reliable and thus, its price increases.

Abstract: A method for fabricating a semiconductor device, capable of simplifying the fabrication, increasing the effective surface area of a charge storage electrode on a limited area, and thereby achieving the fabrication of a highly integrated semiconductor device.

Abstract: A method for fabricating a DRAM cell, capable of obtaining an increased threshold voltage of a metal oxide semiconductor field effect transistor of the DRAM cell, minimizing current leakage and punchthrough phenomenons between adjacent active regions, and increasing the number of unit chips two times by carrying out a lightly doped drain ion implantation in a specific DRAM cell structure for lightly doping a drain while eliminating a high concentration ion implantation.

Abstract: A semiconductor memory device capable of obtaining a sufficient charge storage capacity and yet having a reduced occupied memory cell area. The semiconductor memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulating film formed over the field effect transistor, a first charge storage electrode pattern having a plane plate shape and formed over the interlayer insulating film such that it is electrically connected with the field effect transistor, a second charge storage electrode pattern having a double cylindrical structure and formed over the first charge storage electrode pattern such that it is electrically connected with the first charge storage electrode pattern, and a dielectric film and a plate electrode sequentially formed over the entire exposed surfaces of the first and second charge storage electrode patterns.

Abstract: A method for fabricating a capacitor of a semiconductor memory device, capable of obtaining a sufficient storage capacitance even when a memory cell area is reduced, thereby improving the integration degree of the semiconductor memory device.

Abstract: A semiconductor device and a method of manufacturing the same. In the present invention, the charge storage electrode has a structure in which trenches having a constant width and depth with a constant interval toward the center of the charge storage electrode along the side end of the charge storage electrode are formed, at least one other trench is formed on top of the charge storage electrode surrounding the other trench, and the bottom of the side of the charge storage electrode is shaped as a single step. Accordingly, the present invention can obtain the effect of increasing the efficient surface area of the charge storage electrode by forming at least one trench on the surface of the charge storage electrode, and the resulting increase in capacitance improves the reliability of the device.

Abstract: A method for the fabrication of semiconductor memory device. The method comprises the processes of forming an MOS transistor having an impurity-diffused region of LDD structure at a semiconductor substrate having a P-well (or N-well) therein, forming a two-layer charge storage electrode in such a manner to come into contact with the impurity-diffused region of the MOS transistor, and sequentially forming a dielectric film and a plate electrode on all exposed areas of the two-layer charge storage electrode. The method forms a two-layer structure of charge storage electrode in a DRAM cell, effecting an increase of effective area in the charge storage electrode and improving the degree of integration in a semiconductor memory device.

Abstract: A method for fabricating a capacitor of a semiconductor device, including the steps of: sequentially forming a planarized insulating oxide film, a barrier layer, and a first electrode layer over a semiconductor substrate; forming a first contact hole; forming electrode material spacers respectively on side walls of the first contact hole; forming a second contact hole for exposing an impurity diffusion region of the semiconductor substrate; forming a second electrode layer such that it is in contact with the impurity diffusion region; selectively removing an upper portion of the second electrode layer disposed around a region where the first contact hole is defined, thereby forming a second-electrode layer pattern; forming oxide film spacers on side walls of the second-electrode layer pattern; etching the second-electrode layer pattern, the second electrode layer and the first electrode layer until an upper surface of the barrier layer is exposed, thereby forming a first-electrode layer pattern and outer and

Abstract: There is disclosed a method for the fabrication of capacitor, comprising the steps of: planing an insulating film formed over a transistor and contacting a polysilicon film for charge storage electrode with an active region of the transistor; forming a photosensitive film pattern with a predetermined size over the polysilicon film and forming a spacer insulating film at each of the side walls of the photosensitive film pattern; subjecting the polysilicon film to etch, so as to thin it partly, in the state of using the photosensitive film pattern and the spacer insulating films as an etch mask; removing the photosensitive film pattern and forming a polysilicon film for spacer with a certain thickness over the resulting structure; etching the polysilicon film for spacer, to form a spacer polysilicon film at each of the side walls of the spacer insulating film; subjecting the polysilicon film for charge storage electrode to etch in the state of using the spacer insulating film and the spacer polysilicon film to

Abstract: There is disclosed a method for fabricating a capacitor of semiconductor memory device, capable of securing an electrostatic capacity useful to high integration of semiconductor device. In accordance with the method, a contact pad, a first polysilicon film, a second polysilicon film and a third polysilicon film are utilized as a charge storage electrode, so that the charge storage electrode's surface area comes to be enlarged, bringing about increasing the capacity. In addition, a plate electrode is made by forming an empty region within the charge storage electrode, so that the resulting charge storage electrode can be maximized in capacity by the method. Consequently, a highly integrated DRAM cell can be fabricated and the memory device reliability can be improved, in accordnce with the present invention.

Abstract: A semiconductor memory device and a method for manufacturing the same, capable of increasing the effective cell capacitor area by virtue of steps each defined between a semiconductor substrate surface and each field oxide film formed over the semiconductor substrate. Over the semiconductor substrate, a thin film MOSFET is formed, which includes a charge storage electrode and an active region both connected with a charge storage electrode of each memory cell through a charge storage contact hole. With this structure, a second effective capacitor area is obtained, thereby enabling the capacitance to increase. Also, the semiconductor substrate is connected with a substrate of the thin film MOSFET by a substrate contact hole. Accordingly, it is possible to control the electrical characteristic of the thin film MOSFET. In spite of a decrease in cell area, a higher charge storage capacity can be also obtained.