Abstract: Embodiments relate to a method for manufacturing a semiconductor device that may be capable of obtaining a stable device characteristic by securing an optimal CD of a gate. In embodiments, a method may include forming a gate oxide layer on a semiconductor substrate, forming a photoresist pattern at a first region of an upper portion of the gate oxide layer, forming an insulating layer on the substrate of a second region except for the photoresist pattern, removing the photoresist pattern after a formation of the insulating layer, forming a polysilicon on the substrate from which the photoresist pattern is removed, planarizing the polysilicon to expose the insulating layer in order to form a gate, forming sidewalls at both sides of the gate: and implanting ions in a resulting object using the sidewalls as a mask to form source/drain.

Abstract: Embodiments relate to a method for forming a fine pattern of a semiconductor device. According to embodiments, the method for forming a fine pattern of a semiconductor device may include forming a first oxide layer on a semiconductor substrate, forming a photoresist pattern on the first oxide layer, forming a second oxide layer on the first oxide layer exposed by the photoresist pattern, exposing the first oxide layer through a gap of the second oxide layer by removing the photoresist pattern, forming a spacer layer on sidewalls of the second oxide layer exposing the first oxide layer, forming a target layer for a fine pattern on the first oxide layer exposed by the second oxide layer and the spacer layer, and forming a fine pattern having a pitch reduced within a thickness range of the spacer layer by performing planarization with respect to the second oxide layer, the spacer layer, and the target layer for the fine pattern.

Abstract: A DRAM capacitor and a method for fabricating the same, capable of achieving an increase in surface area and thereby an increase in capacitance while reducing the topology, by simply forming a conduction layer, as a charge storage electrode, comprised of conduction spacers around a double-layer pin-shaped conduction layer pattern or a combination of a central conduction layer pattern and an outer conduction layer pattern having an upwardly-opened dome structure surrounding the central conduction layer pattern, using an etch rate difference between insulating films.

Abstract: A method for fabricating a semiconductor device comprises the steps of depositing polysilicon on a semiconductor substrate for a gate electrode and word line and then depositing insulating oxide layer thickly over the polysilicon. The method forms fine patterns accurately, and forms the contact hole and the gate electrode simultaneously, which prevents short circuit between conductors. The method also reduces the defects or particles which are frequently generated in prior mask and polysilicon and polysilicon spacer processes, so that the reliability and production yield of semiconductor devices may be improved.