Abstract: A display device includes a display panel, a gate driver, and a driving controller. The display panel includes a pixel. The gate driver applies an anode initialization signal to the pixel. The driving controller receives a horizontal synchronization signal, receives input image data at a variable frame frequency, and controls the gate driver. A frame period for the display panel includes a scan period and one or more hold periods, the driving controller generates a count value by counting a number of pulses of the horizontal synchronization signal, and determines a current frame period as the hold period when the count value exceeds a reference value, and a time length of the anode initialization signal in each of the one or more hold periods is longer than a time length of the anode initialization signal in the scan period.

Abstract: A display device, includes: a display panel including a pixel electrically coupled to a gate line and a data line; a gate driver configured to provide a gate signal to the gate line; and a data driver configured to provide a data signal to the data line, wherein the gate driver is configured to sequentially provide a first gate signal and a second gate signal to the gate line during a first frame period, wherein the data driver is configured to provide a first data signal to the data line in response to the first gate signal, and to provide a second data signal to the data line in response to the second gate signal, and wherein the second data signal is different from the first data signal and varies dependent on the first data signal.

Abstract: A display device includes a base layer including a first surface and a second surface, a first line disposed on the first surface of the base layer, a second line corresponding to the first line and disposed on the second surface of the base layer, and a connection film electrically contacting at least a portion of the second line and electrically connected to a printed circuit board and a driving circuit. The driving circuit is disposed between the printed circuit board and the connection film.

Abstract: A pixel includes a first transistor connected between a first power line and a first node, and including a gate electrode connected to a second node, a second transistor connected between a data line and the second node, and including a gate electrode connected to a scan line, a third transistor connected between a first sensing line and the first node, and including a gate electrode connected to a first control line, a fourth transistor connected between a second sensing line and a third node, and including gate electrode connected to a second control line, a first sub light emitting unit including light emitting elements connected in parallel in a forward direction between the first node and the third node, and a second sub light emitting unit including light emitting elements connected in parallel in the forward direction between the third node and a second power line.

Abstract: A display device, includes: a display panel including a pixel electrically coupled to a gate line and a data line; a gate driver configured to provide a gate signal to the gate line; and a data driver configured to provide a data signal to the data line, wherein the gate driver is configured to sequentially provide a first gate signal and a second gate signal to the gate line during a first frame period, wherein the data driver is configured to provide a first data signal to the data line in response to the first gate signal, and to provide a second data signal to the data line in response to the second gate signal, and wherein the second data signal is different from the first data signal and varies dependent on the first data signal.

Abstract: A display device includes: pixels, each of the pixels including at least one light emitting element and a first transistor configured to supply a driving current to the at least one light emitting element; a sensing unit configured to sense a driving current of the first transistor, which corresponds to a data voltage applied to one pixel from among the pixels, the sensing unit being configured to detect a luminance of the light emitting element, which corresponds to the driving current; a gamma calculator configured to receive the driving current and the luminance of the light emitting element from the sensing unit, to calculate a gamma changed based on the driving current and the luminance of the light emitting element, and to provide, to a memory, the gamma changed based on the driving current and the luminance of the light emitting element.

Abstract: A display device includes a pixel. The pixel includes an emission unit and a pixel circuit. The pixel circuit to provide a first driving current to the emission unit in a first current flowing direction in a first mode, and to provide a second driving current to the emission unit in a second current flowing direction different from the first current flowing direction in a second mode. The emission unit includes a first electrode and a second electrode spaced from each other, a first light emitting element connected between the first electrode and the second electrode in the first current flowing direction, and a second light emitting element connected between the first electrode and the second electrode in the second current flowing direction.

Abstract: A display device includes a pixel. The pixel includes an emission unit and a pixel circuit. The pixel circuit to provide a first driving current to the emission unit in a first current flowing direction in a first mode, and to provide a second driving current to the emission unit in a second current flowing direction different from the first current flowing direction in a second mode. The emission unit includes a first electrode and a second electrode spaced from each other, a first light emitting element connected between the first electrode and the second electrode in the first current flowing direction, and a second light emitting element connected between the first electrode and the second electrode in the second current flowing direction.

Abstract: A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

Abstract: A display device may include first-type gate lines, second-type gate lines, a data line, and a pixel. The first-type gate lines include a first gate line. The second-type gate lines include a second gate line and traverse the first gate line. The pixel includes a first switching transistor and a second switching transistor. The first switching transistor includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is electrically connected to the first gate line. The first source electrode is electrically connected to the data line. The second switching transistor includes a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is electrically connected to the second gate line. The second source electrode is electrically connected to the first drain electrode.

Abstract: A display device includes: a driving voltage provider for generating a PWM signal according to the frequency of a clock signal, and providing a driving voltage generated according to the duty ratio of the PWM signal to at least one of the pixels, the data driver, and the scan driver. The driving voltage provider tunes the frequency of the clock signal to a first frequency in a first section, tunes the frequency of the clock signal to a second frequency smaller than the first frequency in a second section in which the magnitude of a driving voltage is larger than that in the first section, and tunes the frequency of the clock signal to a third frequency larger than the first frequency in a third section in which the magnitude of a driving voltage is smaller than that in the first section.

Abstract: A display device includes: a driving voltage provider for generating a PWM signal according to the frequency of a clock signal, and providing a driving voltage generated according to the duty ratio of the PWM signal to at least one of the pixels, the data driver, and the scan driver. The driving voltage provider tunes the frequency of the clock signal to a first frequency in a first section, tunes the frequency of the clock signal to a second frequency smaller than the first frequency in a second section in which the magnitude of a driving voltage is larger than that in the first section, and tunes the frequency of the clock signal to a third frequency larger than the first frequency in a third section in which the magnitude of a driving voltage is smaller than that in the first section.

Abstract: A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

Abstract: A display device may include first-type gate lines, second-type gate lines, a data line, and a pixel. The first-type gate lines include a first gate line. The second-type gate lines include a second gate line and traverse the first gate line. The pixel includes a first switching transistor and a second switching transistor. The first switching transistor includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is electrically connected to the first gate line. The first source electrode is electrically connected to the data line. The second switching transistor includes a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is electrically connected to the second gate line. The second source electrode is electrically connected to the first drain electrode.

Abstract: A liquid crystal display device is provided as follows. A display panel having a first aspect ratio includes pixels, scan lines and data lines. The pixels are arranged at intersections of the scanning lines and the data lines. A display panel driver, in a partial mode in which an image having a second aspect ratio different from the first aspect ratio is displayed on a partial region of the display panel for two or more frame periods, supplies scan signals only to a first number of scan lines electrically connected to pixels of the partial region for a first type frame period of the two or more frame periods, and supplies scan signals to the plurality of scan lines for a second type frame period of the two or more frame periods.

Abstract: A method of driving a display panel includes: selectively providing a resistance using resistor parts in response to address signals, where the resistor parts have resistances, respectively; and outputting common voltages to the display panel based on the selectively provided resistance.

Abstract: A method of driving a display panel is provided. The method includes displaying a first image on at least one odd-numbered horizontal line of the display panel along a first direction and a second direction during a first period of a frame period and displaying a second image on at least one even-numbered horizontal line of the display panel along the first direction and second direction during a second period of the frame period.

Abstract: A method of controlling a driving voltage of a display apparatus includes transmitting a ready signal from a timing control circuit of the display apparatus to a power management circuit of the display apparatus through a connection area of a connection member of the display apparatus, which is disposed between a display panel and a main circuit board of the display apparatus, and controlling a generation of the driving voltage from the power management circuit based on the ready signal received by the power management circuit, where the display apparatus includes a gate driver circuit disposed on the display panel, and the timing control circuit and the power management circuit are disposed on the main circuit board.

Abstract: A method of driving a display panel includes: selectively providing a resistance using resistor parts in response to address signals, where the resistor parts have resistances, respectively; and outputting common voltages to the display panel based on the selectively provided resistance.

Abstract: A power supply of the present disclosure includes: a power generator that generates a first driving voltage to be supplied to a timing controller; and a voltage compensator that performs feedback of the first driving voltage and generates a feedback voltage according to a voltage difference between the first driving voltage and a first reference voltage supplied from the power generator. In this structure, the power generator generates a second driving voltage by boosting or dropping the first driving voltage to correspond to the feedback voltage, and may supply the second driving voltage to the timing controller.