Abstract: A memory device includes a data read/write block configured to store data in memory cells and read data from the memory cells; an input/output buffer block configured to buffer input data inputted through data pads and control signals inputted through control signal pads, and provide buffered input data and control signals to the data read/write block, and buffer read data read out through the data read/write block, and output buffered read data to an external device through the data pads, and a control logic configured to activate or deactivate the input/output buffer block based on an address which is inputted from the external device.

Abstract: Various exemplary embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the memory apparatus may include: a page buffer; an even bit line connected to the page buffer; an odd bit line connected to the page buffer; an even memory cell string installed on the even bit line; an odd memory cell string installed on the odd bit line; and a bit line select unit configured to selectively generate a signal read path between the even bit line and the even memory cell string or between the odd bit line and the odd memory cell string.

Abstract: A semiconductor memory device includes a switching element coupled between a power supply line and an output terminal of a power supply circuit for supplying a power supply voltage, wherein the switching element is configured to be turned on in response to a standby signal, a page buffer including a plurality of latch circuits, wherein a voltage input terminal of at least one of the latch circuits is coupled to the output terminal of the power supply circuit and a voltage input terminal of at least another one of the latch circuits is coupled to the power supply line, and a control logic circuit configured to generate the standby signal according to an operation mode of the semiconductor memory device.

Abstract: Various exemplary embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the memory apparatus may include: a page buffer; an even bit line connected to the page buffer; an odd bit line connected to the page buffer; an even memory cell string installed on the even bit line; an dd memory cell string installed on the odd bit line; and a bit line select unit configured to selectively generate a signal read path between the even bit line and the even memory cell string or between the odd bit line and the odd memory cell string.