Patents by Inventor Eui-Seong Hwang

Eui-Seong Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9484335
    Abstract: A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 1, 2016
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Eun-Shil Park, Tae-Yoon Kim, Ju-Hyun Myung, Kyu-Hyung Yoon
  • Patent number: 9443858
    Abstract: A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the semiconductor bodies and including a metal silicide; and barrier layers formed under and over the buried bit lines and containing germanium.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: September 13, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ju-Hyun Myung, Eui-Seong Hwang, Eun-Shil Park, Tae-Yoon Kim
  • Patent number: 9379117
    Abstract: A method for fabricating a semiconductor device includes etching semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: June 28, 2016
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Eun-Shil Park
  • Publication number: 20160086957
    Abstract: A method for fabricating a semiconductor device includes etching semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 24, 2016
    Inventors: Heung-Jae CHO, Eui-Seong HWANG, Eun-Shil PARK
  • Patent number: 9287169
    Abstract: A semiconductor device includes body lines, formed substantially perpendicular to a substrate, and having recessed sidewalls, buried bit lines, buried in the recessed sidewalls, and including a metal silicide, and a barrier layer interposed between each of the buried bit lines and the body lines corresponding thereto, and containing germanium.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: March 15, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ju-Hyun Myung, Eui-Seong Hwang, Eun-Shil Park, Tae-Yoon Kim
  • Patent number: 9245976
    Abstract: A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: January 26, 2016
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Eun-Shil Park
  • Patent number: 9236386
    Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: January 12, 2016
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Eun-Shil Park
  • Patent number: 9087856
    Abstract: A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: July 21, 2015
    Assignee: SK Hynix Inc.
    Inventor: Eui-Seong Hwang
  • Publication number: 20150140808
    Abstract: A semiconductor device includes body lines, formed substantially perpendicular to a substrate, and having recessed sidewalls, buried bit lines, buried in the recessed sidewalls, and including a metal silicide, and a barrier layer interposed between each of the buried bit lines and the body lines corresponding thereto, and containing germanium.
    Type: Application
    Filed: December 10, 2014
    Publication date: May 21, 2015
    Inventors: Ju-Hyun MYUNG, Eui-Seong HWANG, Eun-Shil PARK, Tae-Yoon KIM
  • Publication number: 20150091070
    Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.
    Type: Application
    Filed: December 9, 2014
    Publication date: April 2, 2015
    Inventors: Heung-Jae CHO, Eui-Seong HWANG, Eun-Shil PARK
  • Publication number: 20150079744
    Abstract: A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Inventor: Eui-Seong HWANG
  • Publication number: 20150079767
    Abstract: A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the semiconductor bodies and including a metal silicide; and barrier layers formed under and over the buried bit lines and containing germanium.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 19, 2015
    Inventors: Ju-Hyun MYUNG, Eui-Seong HWANG, Eun-Shil PARK, Tae-Yoon KIM
  • Publication number: 20150031180
    Abstract: A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.
    Type: Application
    Filed: October 10, 2014
    Publication date: January 29, 2015
    Inventors: Heung-Jae CHO, Eui-Seong HWANG, Eun-Shil PARK
  • Patent number: 8936982
    Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 20, 2015
    Assignee: SK hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Eun-Shil Park
  • Patent number: 8921930
    Abstract: A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Eui-Seong Hwang
  • Patent number: 8912604
    Abstract: A semiconductor device includes body lines, formed substantially perpendicular to a substrate, and having recessed sidewalls, buried bit lines, buried in the recessed sidewalls, and including a metal silicide, and a barrier layer interposed between each of the buried bit lines and the body lines corresponding thereto, and containing germanium.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventors: Ju-Hyun Myung, Eui-Seong Hwang, Eun-Shil Park, Tae-Yoon Kim
  • Patent number: 8907409
    Abstract: A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the semiconductor bodies and including a metal silicide; and barrier layers formed under and over the buried bit lines and containing germanium.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Ju-Hyun Myung, Eui-Seong Hwang, Eun-Shil Park, Tae-Yoon Kim
  • Patent number: 8906775
    Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Tae-Yoon Kim, Kyu-Hyung Yoon
  • Patent number: 8860127
    Abstract: A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: October 14, 2014
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Eun-Shil Park
  • Publication number: 20140110781
    Abstract: A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.
    Type: Application
    Filed: December 31, 2013
    Publication date: April 24, 2014
    Applicant: SK hynix Inc.
    Inventor: Eui-Seong HWANG