Abstract: A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a comparator. The sensing voltage generator outputs a sensing voltage to a sensing node depending on a current flowing through a data line. A load transistor supplying a current to the data line is directly connected to a clamping node. The load transistor is included in a current mirror circuit. In a read operation, a low voltage drive operation is performed and a sensing speed and power consumption are properly controlled.

Abstract: An integrated includes a memory cell, a bit line connected to the memory cell, a boosting circuit to boost the bit line up to a boosting voltage during a pre-charge operation pre-charging the bit line, and a regulation circuit connected between the bit line and an output terminal and determines a logic level of the output terminal according to the voltage of the bit line.

Abstract: A semiconductor device includes a test pattern decoding unit and a scan chain unit. The test pattern receives a scan-in pattern from an external test device and generates a test pattern based on the scan-in pattern and a scan-out pattern. The scan-in pattern is decoded based on a seed pattern and an expectation pattern. The scan chain unit performs logical operation based on the test pattern and feedbacks the scan-out pattern to the test pattern decoding unit.

Abstract: An integrated includes a memory cell, a bit line connected to the memory cell, a boosting circuit to boost the bit line up to a boosting voltage during a pre-charge operation pre-charging the bit line, and a regulation circuit connected between the bit line and an output terminal and determines a logic level of the output terminal according to the voltage of the bit line.

Abstract: A semiconductor device includes a test pattern decoding unit and a scan chain unit. The test pattern receives a scan-in pattern from an external test device and generates a test pattern based on the scan-in pattern and a scan-out pattern. The scan-in pattern is decoded based on a seed pattern and an expectation pattern. The scan chain unit performs logical operation based on the test pattern and feedbacks the scan-out pattern to the test pattern decoding unit.

Abstract: An integrated circuit (IC) is provided. The IC includes a scan controller and a target logic circuit configured to receive a scan input pattern in response to a control of the scan controller, to execute an operation according to the scan input pattern, and to output an execution result. The scan controller compares the execution result with a scan output pattern and outputs a comparison result. The IC can perform a scan test on a particular block that is not controlled by a CPU in a smart card without an additional pad.

Abstract: A smart card system having: a smart card including a security logic circuit to detect an external attack; and a reader communicating with the smart card. The security logic circuit detects the external attack by measuring the external input capacitance through an input/output pad of the smart card and comparing the external input capacitance to the input capacitance of the reader. This improves the security of the smart card system.

Abstract: An amplitude-shift-keying radio-frequency (ASK RF) signal decoding method includes separating a low frequency and a high frequency from an ASK RF signal, which includes a pause section and a non-pause section, generating a divided signal by dividing the high frequency signal, counting the divided signal for the non-pause section of the low frequency signal, and decoding the ASK RF signal based on a result of the counting.

Abstract: An amplitude-shift-keying radio-frequency (ASK RF) signal decoding method includes separating a low frequency and a high frequency from an ASK RF signal, which includes a pause section and a non-pause section, generating a divided signal by dividing the high frequency signal, counting the divided signal for the non-pause section of the low frequency signal, and decoding the ASK RF signal based on a result of the counting.

Abstract: A relaxation oscillator compensates for system delay. The relaxation oscillator includes first and second input signal units that generates first and second capacitor voltages, a delay compensation unit that receives a reference voltage and the first and second capacitor voltages and that generates a compensation voltage. In certain embodiments, a voltage generating unit applies the reference voltage to the delay compensation unit, and a latch unit stores first and second comparison signals compared by the first and second input signal units and transmits a clock signal and a inverted clock signal to the first and second input signal units. The first and second input signal units compare the first and second capacitor voltages with a compensation voltage transmitted from the delay compensation unit.

Abstract: An integrated circuit (IC) device is provided. The IC device includes a detector configured to detect an abnormal condition of the IC device and to generate a detection result as an attack signal, and a noise filter configured to filter out the attack signal as noise and to generate a filtered attack signal. The noise filter is configured to filter out the attack signal as noise when the attack signal is not maintained at a first logic level for a reference period and to generate the filtered attack signal when the attack signal is maintained at the first logic level for the reference period.

Abstract: A smart card system having: a smart card including a security logic circuit to detect an external attack; and a reader communicating with the smart card. The security logic circuit detects the external attack by measuring the external input capacitance through an input/output pad of the smart card and comparing the external input capacitance to the input capacitance of the reader. This improves the security of the smart card system.

Abstract: A relaxation oscillator compensates for system delay. The relaxation oscillator includes first and second input signal units that generates first and second capacitor voltages, a delay compensation unit that receives a reference voltage and the first and second capacitor voltages and that generates a compensation voltage. In certain embodiments, a voltage generating unit applies the reference voltage to the delay compensation unit, and a latch unit stores first and second comparison signals compared by the first and second input signal units and transmits a clock signal and a inverted clock signal to the first and second input signal units. The first and second input signal units compare the first and second capacitor voltages with a compensation voltage transmitted from the delay compensation unit.

Abstract: Voltage glitch detection circuits and methods thereof. The voltage glitch detection circuit may include a monitoring memory array including at least one memory cell storing reference data, a monitoring sense amplifier receiving stored reference data from the monitoring memory array, amplifying the received stored reference data in response to an operation control signal and outputting data based on the reference data, a data storage circuit including at least one latch to store the reference data and a comparator circuit receiving and comparing the data output from the monitoring sense amplifier and the stored reference data from the data storage circuit, and outputting a detection signal based on the comparison.

Abstract: A demodulator for processing a PWM (pulse width modulation) signal includes a variable capacitor, a charging unit, a discharging unit, and a tuner. The charging and discharging units charge or discharge the variable capacitor depending on the PWM signal. The tuner determines a capacitance of the variable capacitor and a discharge current of the discharging unit for proper operation of the demodulator in various RF environments.

Abstract: An amplitude-shift-keying radio-frequency (ASK RF) signal decoding method includes separating a low frequency and a high frequency from an ASK RF signal, which includes a pause section and a non-pause section, generating a divided signal by dividing the high frequency signal, counting the divided signal for the non-pause section of the low frequency signal, and decoding the ASK RF signal based on a result of the counting.

Abstract: A system having a virtual direct memory access (DMA) and a driving method thereof, in which the system includes a central processing unit (CPU), a plurality of intellectual property units (IPs), and a virtual DMA controlling data to be transferred from a first IP unit to a second IP unit according to select information that, selects the first and second IP units of the plurality of IP units, wherein the CPU provides the select information to the virtual DMA. As an example, the first IP transfers data and the second IP receives the data.

Abstract: A security apparatus within a smart card includes a plurality of security blocks with at least one shared component. Each security block that when activated generates a respective output signal indicating whether a respective detected parameter is within a respective acceptable range. A selecting unit couples the shared component to the activated one of the security blocks for minimized area and cost of the security apparatus.

Abstract: An internal voltage converter and method is provided capable of reducing power consumption using a selective voltage reference, a semiconductor device including the internal voltage converter. A semiconductor device uses the internal voltage converter which discriminates an IVC stand-by state from a normal operation state, selects a voltage reference with low power consumption among selective voltage references in the IVC stand-by state, and generates an internal voltage.

Abstract: A demodulator for processing a PWM (pulse width modulation) signal includes a variable capacitor, a charging unit, a discharging unit, and a tuner. The charging and discharging units charge or discharge the variable capacitor depending on the PWM signal. The tuner determines a capacitance of the variable capacitor and a discharge current of the discharging unit for proper operation of the demodulator in various RF environments.