Abstract: A display device includes: a pixel circuit layer including a plurality of transistors; first partition wall and a second partition wall on the pixel circuit layer, each of the first and second partition walls having a shape protruding in a thickness direction; a first electrode and a second electrode on the same layer and respectively on the first partition wall and the second partition wall; a light emitting element between the first electrode and the second electrode; and a semiconductor pattern directly on the first electrode.

Abstract: A display device includes: a first substrate; a second substrate on the first substrate and exposing a first edge portion of the first substrate, the second substrate protruding beyond a second edge portion of the first substrate; a connection line on the first edge portion of the first substrate, the connection line having a first end portion protruding beyond a first side of the second substrate and a second end portion covered by the second substrate; and a thin-film transistor layer on the second substrate and connected to the connection line. The thin-film transistor layer includes signal lines extending from the first side to a second side of the second substrate. The signal lines extend into contact openings in the thin-film transistor layer and are exposed at a lower part of the second substrate on the second side of the second substrate.

Abstract: Disclosed is a functional pillow made of a material having elasticity. The functional pillow helps a user sleep in a correct sleeping position in which the user maintains a proper arrangement and angle of the cervical spine while sleeping in any sleeping environment, including on a hard floor or on a soft bed. The functional pillow includes a shoulder protecting portion, a cervical spine protecting portion, and a head protecting portion. The cervical spine protecting portion includes a cervical spine support that inclines upward in a front support portion which is relatively near a body side and inclines downward in a rear support portion which is relatively near a head. The inclination angle of the rear portion and the height of the pillow at the highest point are differently set depending on use of the pillow.

Abstract: A data output circuit in an NAND flash memory device is disclosed. The data path circuit in a flash memory includes at least one switching means configured to output one or more internal address signals in accordance with a data output control signal, and one or more data output circuit configured to output data when a specific internal address signal is outputted through the switching means.

Abstract: A data output circuit in an NAND flash memory device is disclosed. The data path circuit in a flash memory includes at least one switching means configured to output one or more internal address signals in accordance with a data output control signal, and one or more data output circuit configured to output data when a specific internal address signal is outputted through the switching means.

Abstract: Disclosed are a method of controlling a page buffer having a dual register and a control circuit thereof. In the present invention, during a normal program operation, a normal program operation is performed through the same transmission path as a data transmission path along which data is outputted from bit lines of a memory cell array to a YA pad according to a signal PBDO used in a read operation. A program operating time can be reduced and the whole program operation of a chip can be thus reduced. It is also possible to reduce current consumption by shortening a data path during the normal program operation.

Abstract: A redundancy circuit for a NAND flash memory device reduces a test time and production time of the device, by performing a redundancy operation through a repair select unit using a cam cell. In addition, the redundancy circuit employs a repair method using a redundancy cam which can perform the repair operation much faster than a general repair method using fuse cutting.

Abstract: A page buffer in which the value of data that have been latched in a register of a page buffer is not changed by slowly transmitting data to the register in a check board program operation of a NAND flash memory device. The page buffer includes a first register having a first input unit for alternately receiving program data and erase data, and a second register having a second input unit for alternately receiving program data and erase data. Charge devices are respectively coupled to the first and second input units so that the program data or erase data are slowly input to the first or second input unit.

Abstract: A boosting circuit is provided that includes a reference voltage generating circuit unit to generate a reference voltage, a voltage boosting circuit to output a given boosting voltage, and a sensing circuit to sense a flash memory cell according to the reference voltage and the boosting voltage of the voltage boosting circuit. An output signal of the sensing circuit is changed depending on the boosting voltage of the voltage boosting circuit applied to a gate terminal of the flash memory cell. The boosting circuit also includes a switching circuit to apply the boosting voltage of the voltage boosting circuit or a power supply voltage depending on the boosting voltage of the voltage boosting circuit and the output signal of the sensing circuit.

Abstract: The present invention discloses a method and device for preserving a word line pass bias using a ROM block in a NAND-type flash memory. The method for preserving the word line pass bias includes a step for closing a precharge transistor of a precharge circuit before the operation of a pass transistor for precharging a selected word line, by separately outputting from the ROM block a program precharge control signal transmitted to a group access signal generation circuit for outputting a group access signal and a program precharge control signal transmitted to a block word line, and synchronizing the signals in a synchronization circuit. Accordingly, time mismatching in the program and read operations of the NAND-type flash memory is prevented, and a predetermined voltage precharged to the selected block word line is precisely inputted to a specific cell and preserved.

Abstract: A boosting circuit is disclosed.

Abstract: A boosting circuit is disclosed.