Abstract: An electronic device including: a memory; and a processor connected to the memory and configured to execute at least one instruction, wherein the processor executes the at least one instruction to transmit indicator information to the memory, wherein the indicator information identifies one or more memory areas, among a plurality of memory areas included in the memory, where useless data is stored, and the memory skips a writeback for the one or more memory areas, in response to the indicator information.

Abstract: A multi-core processor according to some example embodiments may be a multi-core processor including a plurality of cores, and may include a first core that receives a task migration instruction, and transmits metadata including branch prediction data obtained during execution of a migration subject task determined as a subject of the task migration instruction among a plurality of tasks, to an external memory, and a second core that receives a task execution instruction, and reads the metadata from the external memory on the basis of the task execution instruction, and executes the migration subject task using the metadata.

Abstract: A cache includes a data memory, a tag memory, and a cache controller. The data memory includes a stack area storing, in a stack structure, data used by an external processor in a plurality of cache lines. The tag memory stores a tag entry including useless information indicating whether data stored in a corresponding cache line has been popped. The cache controller is configured to, when a pop request for data stored in the stack area is received, change the useless information of a cache line storing the data subject to the pop request, to a useless state.

Abstract: An electronic device including a main memory, a plurality of caches that are hierarchically connected, the plurality of caches configured to store part of data stored in the main memory, and processing circuitry configured to transmit a memory request for desired data to the plurality of caches and the main memory, the memory request including cache allocation range information associated with the desired data, and each of the plurality of caches are configured to, determine whether to perform an operation corresponding to the memory request based on the cache allocation range information.

Abstract: An integrated circuit includes a plurality of combinational logic circuits, a scan chain circuit including a plurality of sequential logic circuits configured to store output values of the plurality of combinational logic circuits in synchronization with a first clock signal and sequentially provide first output values stored at a first time point in synchronization with a second clock signal, and control circuitry configured to receive the first output values as input values and sequentially provide the input values to the scan chain circuit. The plurality of sequential logic circuits are configured to store first input values at a second time point passed occurring when a first cycle of the second clock signal passes. The first input values are the same as the first output values.