Patents by Inventor Euiyoung JEONG

Euiyoung JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908807
    Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate with first-conductivity-type impurities; first and second active regions provided on the substrate; a first deep element isolation layer surrounding the first active region; a second deep element isolation layer surrounding the second active region; a suction region surrounding the first and second deep element isolation layers, the suction region including the first-conductivity-type impurities; a well region provided in the substrate between the first and second active regions, the well region including second-conductivity-type impurities different from the first-conductivity-type impurities; a shallow element isolation layer provided between the suction region and the well region; and a guard structure connected to the suction region. The substrate includes a signal path portion that is provided between a top surface of the substrate and the well region, and surrounds an upper portion of the well region.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Huichul Shin, Hyungjin Lee, Jinhong Park, Mingeun Song, Euiyoung Jeong, Hiroki Fujii
  • Publication number: 20220399284
    Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate with first-conductivity-type impurities; first and second active regions provided on the substrate; a first deep element isolation layer surrounding the first active region; a second deep element isolation layer surrounding the second active region; a suction region surrounding the first and second deep element isolation layers, the suction region including the first-conductivity-type impurities; a well region provided in the substrate between the first and second active regions, the well region including second-conductivity-type impurities different from the first-conductivity-type impurities; a shallow element isolation layer provided between the suction region and the well region; and a guard structure connected to the suction region. The substrate includes a signal path portion that is provided between a top surface of the substrate and the well region, and surrounds an upper portion of the well region.
    Type: Application
    Filed: January 12, 2022
    Publication date: December 15, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Huichul SHIN, Hyungjin LEE, Jinhong PARK, Mingeun SONG, Euiyoung JEONG, Hiroki FUJII