Patents by Inventor EULA A. TOLENTINO
EULA A. TOLENTINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10838728Abstract: Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.Type: GrantFiled: September 24, 2018Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Kurt A. Feiste, Christopher M. Mueller, Dung Q. Nguyen, Eula A. Tolentino, Tien T. Tran, Jing Zhang
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Patent number: 10564691Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Patent number: 10528347Abstract: Executing system call vectored (SCV) instructions in a multi-slice processor including receiving, by an instruction fetch unit, a SCV instruction, wherein the SCV instruction is a system call from an operating system; sending the SCV instruction to a branch issue queue; determining, by the branch issue queue, that the SCV instruction is next-to-complete; issuing the SCV instruction to a branch resolution unit; and executing the SCV instruction by the branch resolution unit.Type: GrantFiled: May 16, 2018Date of Patent: January 7, 2020Assignee: International Business Machines CorporporationInventors: Susan E. Eisen, Nicholas R. Orzol, Mehul Patel, Eula A. Tolentino
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Patent number: 10296337Abstract: Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.Type: GrantFiled: March 21, 2016Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Patent number: 10209757Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: November 2, 2017Date of Patent: February 19, 2019Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Publication number: 20190026112Abstract: Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.Type: ApplicationFiled: September 24, 2018Publication date: January 24, 2019Inventors: Kurt A. Feiste, Christopher M. Mueller, Dung Q. Nguyen, Eula A. Tolentino, Tien T. Tran, Jing Zhang
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Patent number: 10102001Abstract: Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.Type: GrantFiled: March 28, 2018Date of Patent: October 16, 2018Assignee: International Business Machines CorporationInventors: Kurt A. Feiste, Christopher M. Mueller, Dung Q. Nguyen, Eula A. Tolentino, Tien T. Tran, Jing Zhang
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Publication number: 20180260224Abstract: Executing system call vectored (SCV) instructions in a multi-slice processor including receiving, by an instruction fetch unit, a SCV instruction, wherein the SCV instruction is a system call from an operating system; sending the SCV instruction to a branch issue queue; determining, by the branch issue queue, that the SCV instruction is next-to-complete; issuing the SCV instruction to a branch resolution unit; and executing the SCV instruction by the branch resolution unit.Type: ApplicationFiled: May 16, 2018Publication date: September 13, 2018Inventors: SUSAN E. EISEN, NICHOLAS R. ORZOL, MEHUL PATEL, EULA A. TOLENTINO
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Patent number: 10048963Abstract: Executing system call vectored (SCV) instructions in a multi-slice processor including receiving, by an instruction fetch unit, a SCV instruction, wherein the SCV instruction is a system call from an operating system; sending the SCV instruction to a branch issue queue; determining, by the branch issue queue, that the SCV instruction is next-to-complete; issuing the SCV instruction to a branch resolution unit; and executing the SCV instruction by the branch resolution unit.Type: GrantFiled: May 23, 2016Date of Patent: August 14, 2018Assignee: International Business Machines CorporationInventors: Susan E. Eisen, Nicholas R. Orzol, Mehul Patel, Eula A. Tolentino
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Publication number: 20180217842Abstract: Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.Type: ApplicationFiled: March 28, 2018Publication date: August 2, 2018Inventors: Kurt A. Feiste, Christopher M. Mueller, Dung Q. Nguyen, Eula A. Tolentino, Tien T. Tran, Jing Zhang
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Publication number: 20180088653Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: ApplicationFiled: November 2, 2017Publication date: March 29, 2018Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
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Patent number: 9928073Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.Type: GrantFiled: February 22, 2016Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Patent number: 9921833Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.Type: GrantFiled: December 15, 2015Date of Patent: March 20, 2018Assignee: International Business Machines CorporationInventors: Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Publication number: 20180074565Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: ApplicationFiled: November 3, 2017Publication date: March 15, 2018Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
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Patent number: 9870045Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: February 17, 2016Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Patent number: 9870039Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: December 15, 2015Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Publication number: 20180004527Abstract: Operation of a computer processor that includes: receiving a first instruction indicating a first target register; receiving, from an instruction fetch unit of the computer processor, a first instruction and a branch instruction; responsive to determining that the branch instruction is dependent upon a result of the first instruction, updating a priority value corresponding to the first instruction; and issuing, in dependence upon the priority value for the first instruction having a higher priority than a priority value for another instruction, the first instruction to an execution unit of the computer processor.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: KHANDKER N. ADEEB, JOSHUA W. BOWMAN, BRANDON R. GODDARD, DUNG Q. NGUYEN, TU-AN T. NGUYEN, EULA A. TOLENTINO, BRIAN D. VICTOR, BRENDAN M. WONG
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Publication number: 20170337058Abstract: Executing system call vectored (SCV) instructions in a multi-slice processor including receiving, by an instruction fetch unit, a SCV instruction, wherein the SCV instruction is a system call from an operating system; sending the SCV instruction to a branch issue queue; determining, by the branch issue queue, that the SCV instruction is next-to-complete; issuing the SCV instruction to a branch resolution unit; and executing the SCV instruction by the branch resolution unit.Type: ApplicationFiled: May 23, 2016Publication date: November 23, 2017Inventors: SUSAN E. EISEN, NICHOLAS R. ORZOL, MEHUL PATEL, EULA A. TOLENTINO
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Publication number: 20170269936Abstract: Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.Type: ApplicationFiled: March 21, 2016Publication date: September 21, 2017Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
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Publication number: 20170168821Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.Type: ApplicationFiled: December 15, 2015Publication date: June 15, 2017Inventors: JOSHUA W. BOWMAN, SUNDEEP CHADHA, MICHAEL J. GENDEN, DHIVYA JEGANATHAN, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO