Abstract: The present invention relates to a composition comprising an egg white combined chalcanthite component for preventing or treating cancer, and more particularly, to a composition for preventing or treating cancer, which comprises egg white combined chalcanthite prepared by mixing a roasted chalcanthite with egg white to reduce the toxicity of the chalcanthite or comprises a mixture of the egg white combined chalcanthite and a bamboo salt, and a method for preparing the same. The composition comprising the egg white combined chalcanthite exhibits excellent anti-cancer activity, and thus is usefully applicable to pharmaceutical preparations for preventing or treating cancer or the manufacture of health functional foods.

Abstract: Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

Abstract: The present invention relates to a composition comprising an egg white-chalcanthite component for preventing or treating cancer, and more particularly, to a composition for preventing or treating cancer, which comprises egg white-chalcanthite prepared by mixing a roasted chalcanthite with egg white to reduce the toxicity of the chalcanthite or comprises a mixture of the egg white-chalcanthite and a bamboo salt, and a method for preparing the same. The composition comprising the egg white-chalcanthite exhibits excellent anti-cancer activity, and thus is usefully applicable to pharmaceutical preparations for preventing or treating cancer or the manufacture of health functional foods.

Abstract: A turbo TCM decoder for performing a soft decision without performing a sector phase quantization is disclosed. The turbo TCM decoder includes: a symbol transformer for converting a received signal to signal bits of QPSK mode by using an I-axis coordinate and a Q-axis coordinate on a constellation of the received signal; a phase sector quantizer for performing a phase sector quantization or the received signal by using the I-axis coordinate and the Q-axis coordinate; a first decoder for determining coded data by decoding the converted signal bits; a delay for delaying the quantized signal; and a second decoder for determining un-coded data by using the delayed quantized signal and the determined coded data.

Abstract: Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

Abstract: A pragmatic trellis code modulation decoder including a demodulator for receiving a modulated signal and computing coordination values of symbols of the modulated signal on an I-axis and Q-axis in a constellation; a coset mapper for generating 3-bit soft decision data based on the computed coordinate values; a viterbi decoder for receiving 3-bit soft decision data and generating 1-bit data as a coded data by decoding the 3-bit soft decision data; a re-encoder for receiving the 1-bit data from the viterbi decoder and obtaining un-coded information in order to compute an un-coded data; a sector phase quantizer for obtaining I channel and Q channel information based on the coordination values from the demodulator in order to obtain un-coded data; a time delayer for delaying output of the sector phase quantizer until the re-encoder outputs the un-coded information; and a non-coded code decoder for computing the un-coded data.

Abstract: The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (?) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.

Abstract: The present invention relates to non-vaccinal and non-pharmacologic compositions and methods for controlling complex retroviral infections. In particular, the present invention provides transgenic animals expressing a transdominant negative Rex gene product that inhibits retroviral replication.

Abstract: Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

Abstract: Provided is a digital satellite broadcasting set-top box and a home network control system employing the same. The set-top box includes: a satellite signal receiving unit for receiving a satellite signal including a home network control signal for controlling the household appliances through a satellite broadcasting network from a remote terminal; and a control unit for extracting a household appliances control signal included in the satellite signal transmitted from the satellite signal receiving unit and commanding a power line converter to transmit the household appliances control signal to a corresponding household appliance, wherein the power line converter converts the household appliances control signal transmitted from the digital satellite broadcasting set-top box into a power line communication signal and transmits the power line communication signal on the home network through a power line.

Abstract: An apparatus for resolution of phase ambiguity is disclosed. The apparatus receives a modulated signal and resolves a phase ambiguity of the modulated signal while recovering the modulated signal to original data, wherein the apparatus includes a phase ambiguity detector for receiving demodulated data and frame synchronization information, and detecting a phase ambiguity value from the demodulated data based on a frame synchronization information; a phase ambiguity eliminator for receiving the phase ambiguity value and the demodulated data, and generating a phase ambiguity eliminated data by inverting the phase ambiguity value and multiplying the inverted phase ambiguity value and the demodulated data. The present invention can resolve a phase ambiguity occurred in various modulation modes including a burst mode communication with the same algorithm so it can effectively be implemented to an adaptive MODEM.

Abstract: Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

Abstract: A turbo TCM decoder for performing a soft decision without performing a sector phase quantization is disclosed. The turbo TCM decoder includes: a symbol transformer for converting a received signal to signal bits of QPSK mode by using an I-axis coordinate and a Q-axis coordinate on a constellation of the received signal; a phase sector quantizer for performing a phase sector quantization or the received signal by using the I-axis coordinate and the Q-axis coordinate; a first decoder for determining coded data by decoding the converted signal bits; a delay for delaying the quantized signal; and a second decoder for determining un-coded data by using the delayed quantized signal and the determined coded data.

Abstract: The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (?) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.

Abstract: The present invention relates to non-vaccinal and non-pharmacologic compositions and methods for controlling complex retroviral infections. In particular, the present invention provides transgenic animals expressing a transdominant negative Rex gene product that inhibits retroviral replication.

Abstract: A pragmatic trellis code modulation decoder is disclosed.

Abstract: A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams.

Abstract: An apparatus for resolution of phase ambiguity is disclosed. The apparatus receives modulated signal and resolves a phase ambiguity of the modulated signal while recovering the modulated signal to original data, wherein the apparatus includes a phase ambiguity detector for receiving demodulated data and frame synchronization information, and detecting a phase ambiguity value from the demodulated data based on a frame synchronization information; a phase ambiguity eliminator for receiving the phase ambiguity value and the demodulated data, and generating a phase ambiguity eliminated data by inverting the phase ambiguity value and multiplying the inverted phase ambiguity value and the demodulated data. The present invention can resolve a phase ambiguity occurred in various modulation modes including a burst mode communication with same algorithm so it can effectively implemented to an adaptive MODEM.

Abstract: Disclosed is a pragmatic decoder for receiving data encoded by an 8-PSK (phase shift keying) trellis encoder, and using a Viterbi decoder to decode the data, which comprises: an 8-PSK demodulator for demodulating signals transmitted by the trellis encoder; a quantizer for receiving signals from the 8-PSK demodulator, and using a constellation mapping configuration with reference to 0 degrees to detect n constellation position sections; and a soft decision unit for using a constellation position section detected by the quantizer to output a soft decision signal for converting it to I and Q signal arrangements needed for Viterbi decoder inputs.

Abstract: A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams. This structure and this method can be applied to a depuncturing process for Radix-4 branch metric calculation of all punctured codes derived from ½code.