Abstract: A memory device includes a plurality of memory cells and a refresh control circuit that generates a refresh row address and performs a refresh operation on memory cells of a row corresponding to the refresh row address. The refresh control circuit includes a row hammer managing circuit that includes a first row address generator that receives first input row addresses during a first monitoring length and determines a first candidate address among the first input row addresses based on a first reference address, a second row address generator that receives second input row addresses during a second monitoring length longer than the first monitoring length and determines a second candidate address among the second input row addresses based on a second reference address, and a row address checker that determines an aggressor row address based on the first candidate address and the second candidate address.

Abstract: A memory device may include an attack row selector configured to receive an activation signal at a first time point, and generate an update signal based on an accumulation value, an attack row register configured to receive an activation row address corresponding to the activation signal, and determine an attack row address based on the update signal and the activation row address, and a victim row determiner configured to determine a victim row address based on the attack row address. The accumulation value may be the number of activation signals received from a second time point before the first time point to the first time point.

Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

Abstract: Disclosed are an apparatus and a method for estimating a parameter of a multi path signal. The apparatus for estimating a parameter of a multi path signal includes: a plurality of pre-processing units configured to pre-process respective reception signals received through a plurality of antennas; a plurality of parameter converting units configured to approximate a parameter set of the respective pre-processed reception signals to have a sparse characteristic in a Doppler frequency and angle of arrival domain; and a parameter estimating unit configured to estimate an angle of arrival for a plurality of reception signals in each frequency region of the Doppler frequency and angle of arrival domain.

Abstract: A transmission and reception method and apparatus for reducing a PAPR in an orthogonal frequency division multiplexing (OFDM) system are provided. A transmission method includes performing constellation rotation with respect to L input data symbols, performing L-point DFT spreading and circular extension on the constellation-rotated L data symbols to be K symbols, performing frequency domain (FD) windowing processing by multiplying the K circular-extended data symbols by a circular filter coefficient, and transmitting the processed data symbols.

Abstract: Disclosed are an apparatus and a method for estimating a parameter of a multi path signal. The apparatus for estimating a parameter of a multi path signal includes: a plurality of pre-processing units configured to pre-process respective reception signals received through a plurality of antennas; a plurality of parameter converting units configured to approximate a parameter set of the respective pre-processed reception signals to have a sparse characteristic in a Doppler frequency and angle of arrival domain; and a parameter estimating unit configured to estimate an angle of arrival for a plurality of reception signals in each frequency region of the Doppler frequency and angle of arrival domain.

Abstract: A transmission and reception method and apparatus for reducing a PAPR in an orthogonal frequency division multiplexing (OFDM) system are provided. A transmission method includes performing constellation rotation with respect to L input data symbols, performing L-point DFT spreading and circular extension on the constellation-rotated L data symbols to be K symbols, performing frequency domain (FD) windowing processing by multiplying the K circular-extended data symbols by a circular filter coefficient, and transmitting the processed data symbols.