Abstract: A data storage device is provided. The data storage device includes a storage medium configured to store data blocks included in a stripe set, and a controller connected to the storage medium and configured to, decode a first data block disposed in a column among the data blocks, during a read operation of the first data block, and read first group data blocks disposed in the column among the data blocks, based on a read failure of the first data block.

Abstract: Disclosed is a drug delivery implant implanted into a bone. The drug delivery implant includes an implant fixture provided with an inlet formed at the upper end thereof and a drug supply cartridge coupled to the fixture, the drug supply cartridge includes a cap to close the inlet of the fixture and a cartridge main body provided under the cap, coupled with the cap and accommodated in the fixture to release a drug, and a cartridge hole to accommodate the cartridge main body and drug channels to guide the drug released from the inside of the cartridge main body to the outside of the fixture are formed in the fixture. The drug delivery implant may continuously administer the drug into bone tissues and mount the drug cartridge together with the cap in the fixture, thus facilitating mount of the drug cartridge in the fixture and replacement of the drug cartridge.

Abstract: A data storage device is provided. The data storage device includes a storage medium configured to store data blocks included in a stripe set, and a controller connected to the storage medium and configured to, decode a first data block disposed in a column among the data blocks, during a read operation of the first data block, and read first group data blocks disposed in the column among the data blocks, based on a read failure of the first data block.

Abstract: A method of reading multi-bit data stored in a memory cell of a flash memory includes attempting to perform hard decision (HD) decoding on output data from the flash memory, and performing soft decision (SD) decoding on the output data when the HD decoding cannot be performed. The performing of the SD decoding includes: changing a maximum number of iterations according to a threshold voltage distribution of the memory cell; and performing the SD decoding based on the changed maximum number of iterations.

Abstract: Disclosed is a drug delivery implant implanted into a bone. The drug delivery implant includes an implant fixture provided with an inlet formed at the upper end thereof and a drug supply cartridge coupled to the fixture, the drug supply cartridge includes a cap to close the inlet of the fixture and a cartridge main body provided under the cap, coupled with the cap and accommodated in the fixture to release a drug, and a cartridge hole to accommodate the cartridge main body and drug channels to guide the drug released from the inside of the cartridge main body to the outside of the fixture are formed in the fixture. The drug delivery implant may continuously administer the drug into bone tissues and mount the drug cartridge together with the cap in the fixture, thus facilitating mount of the drug cartridge in the fixture and replacement of the drug cartridge.

Abstract: A method of estimating a deterioration state of a memory device comprises reading data from selected memory cells connected to a selected wordline of a memory cell array by applying to the selected wordline a plurality of distinct read voltages having values corresponding to at least one valley of threshold voltage distributions of the selected memory cells, generating quality estimation information indicating states of the threshold voltage distributions using the data read from the selected memory cells, and determining a deterioration state of a storage area including the selected memory cells based on the generated quality estimation information.

Abstract: A method of operating a memory controller in a memory system including a nonvolatile memory device includes; erasing memory cells of a target memory block of the non-volatile memory device on a block basis, and then searching for a bad memory cell by a performing an erase verifying operation, comparing a threshold voltage of the bad memory cell to a reference voltage to generate comparison results, and designating as a bad area one of the entire target memory block, and a sub-block of the target memory block in response to the comparison results.

Abstract: A method of reading multi-bit data stored in a memory cell of a flash memory includes attempting to perform hard decision (HD) decoding on output data from the flash memory, and performing soft decision (SD) decoding on the output data when the HD decoding cannot be performed. The performing of the SD decoding includes: changing a maximum number of iterations according to a threshold voltage distribution of the memory cell; and performing the SD decoding based on the changed maximum number of iterations.

Abstract: A method of operating a memory controller in a memory system including a nonvolatile memory device includes; erasing memory cells of a target memory block of the non-volatile memory device on a block basis, and then searching for a bad memory cell by a performing an erase verifying operation, comparing a threshold voltage of the bad memory cell to a reference voltage to generate comparison results, and designating as a bad area one of the entire target memory block, and a sub-block of the target memory block in response to the comparison results.

Abstract: A laser annealing apparatus includes a lens unit configured to transmit a laser beam to be irradiated onto an irradiation target; a lens unit housing accommodating the lens unit and having an opening configured to allow the laser beam to pass through the opening; a blocking plate configured to block at least a portion of the laser beam reflected by the irradiation target after being transmitted through the lens unit to the irradiation target; and a cooling unit between the blocking plate and the lens unit housing.

Abstract: A method of estimating a deterioration state of a memory device comprises reading data from selected memory cells connected to a selected wordline of a memory cell array by applying to the selected wordline a plurality of distinct read voltages having values corresponding to at least one valley of threshold voltage distributions of the selected memory cells, generating quality estimation information indicating states of the threshold voltage distributions using the data read from the selected memory cells, and determining a deterioration state of a storage area including the selected memory cells based on the generated quality estimation information.

Abstract: A laser annealing apparatus includes a lens unit configured to transmit a laser beam to be irradiated onto an irradiation target; a lens unit housing accommodating the lens unit and having an opening configured to allow the laser beam to pass through the opening; a blocking plate configured to block at least a portion of the laser beam reflected by the irradiation target after being transmitted through the lens unit to the irradiation target; and a cooling unit between the blocking plate and the lens unit housing.

Abstract: A non-volatile semiconductor memory device including a memory cell array having a plurality of memory cells coupled to a plurality of bitlines and wordlines, each memory cell being programmed to one of plurality of data storage states. A node is connected to a selected bitline responsive to a storage state in a selected memory cell. A plurality of latched registers is connected to the node to store and output data bits corresponding the storage state, the data bits being assigned to the selected bitline. A circuit is adapted to precharge the selected bitline before sensing the selected memory cell and is adapted to equalize the selected bitline and the node after sensing the selected memory cell.

Abstract: A burst-type random access memory device according to the present invention includes an address generator that receives an initial address to generate a sequence of burst addresses according to either one of a single data rate mode and a double data rate mode. A decoding circuit decodes the burst address thus generated. Therefore, in the memory device are automatically generated a sequence of burst addresses necessary for a sequential/interleaved burst operation of the single data rate mode and the double data rate mode.

Abstract: A non-volatile semiconductor memory device including a memory cell array having a plurality of memory cells coupled to a plurality of bitlines and wordlines, each memory cell being programmed to one of plurality of data storage states. A node is connected to a selected bitline responsive to a storage state in a selected memory cell. A plurality of latched registers is connected to the node to store and output data bits corresponding the storage state, the data bits being assigned to the selected bitline. A circuit is adapted to precharge the selected bitline before sensing the selected memory cell and is adapted to equalize the selected bitline and the node after sensing the selected memory cell.

Abstract: The method for programming a flash memory device includes sequentially loading program data in the page buffer circuit responsive to a first command signal, the first command signal indicating program data input and generating a program voltage responsive to a second command signal, the second command signal indicating programming initiation. EEPROM cells are programmed after the program voltage reaches a predetermined target. All of the programmed EEPROM cells are verified to ensure that they are properly programmed. If the EEPROM cells are not properly programmed, programming is repeated until all of the EEPROM cells are properly programmed. The program voltage is increased in a stepwise manner every time programming is repeated.

Abstract: A clock monitor circuit includes a first and second delay and clock signal generating unit for receiving a clock signal and an inverted clock signal, respectively. The first and second delay and clock signal generating units generate a first and second signals, respectively. A logic sum unit logically-sums the first and second signals to generate a stop clock signal. The clock monitor circuit according to the present invention can monitor the presence of a clock signal irrespective of an operation cycle of the clock signal. Further, the synchronous semiconductor memory device utilizing the clock monitor circuit according to the present invention is adapted to consume electric current only when a clock signal is present. That is, the device does not consume electric current when the clock signal is not present thereby reducing unnecessary waste of electric power in the stand-by mode.

Abstract: The method for programming a flash memory device includes sequentially loading program data in the page buffer circuit responsive to a first command signal, the first command signal indicating program data input and generating a program voltage responsive to a second command signal, the second command signal indicating programming initiation. EEPROM cells are programmed after the program voltage reaches a predetermined target. All of the programmed EEPROM cells are verified to ensure that they are properly programmed. If the EEPROM cells are not properly programmed, programming is repeated until all of the EEPROM cells are properly programmed. The program voltage is increased in a stepwise manner every time programming is repeated.

Abstract: A burst SRAM device is provided having a burst column selection circuit which is activated in accordance with a burst address, in addition to a column selection circuit for selecting columns of a memory cell array capable of storing a binary data. An internal column address portion of an external column address is applied to the column selection circuit as a first burst address signal. The column selection circuit selects at the same time at least two columns in response to the first burst address signal. During a burst read mode, at least two columns are simultaneously selected in response to the first burst address signal, and data stored in the selected cells are simultaneously sensed and amplified by at least two sense amplifiers corresponding to the selected memory cells. The data amplified thus are stored in a data output register. The burst addresses are applied to the burst column selection circuit.

Abstract: A semiconductor memory device for providing a burst mode control signal. The semiconductor memory device includes a first logic circuit for generating a driving signal in response to a first logic level of an externally input write and read control signal and an externally input chip enable signal, a plurality of transition registers for respectively changing the driving signal in synchronization with a first edge of a clock signal to generate changed driving signals, and a second logic circuit for generating the burst mode control signal generated by the logic combination of the changed driving signals in response to a read latency control signal.