Patents by Inventor Eun Dong Kim

Eun Dong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10103117
    Abstract: Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a semiconductor die to the frame with respect to the fiducial mark pattern, encapsulating the semiconductor die with a passivation layer, for reconstituting the semiconductor die as a wafer level, and sequentially forming a metal seed layer, a redistribution layer, an under bump metal (UBM) seed layer, an UBM layer, and a solder ball on a bonding pad of the semiconductor die upward exposed by an opening region of the passivation layer to finish a fan-out type wafer level package.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: October 16, 2018
    Assignee: SFA Semicon Co., Ltd.
    Inventors: Hyun Hak Jung, Eun Dong Kim, Jong Won Lee, Jai Kyoung Choi, Byeong Ho Jeong
  • Patent number: 10050499
    Abstract: Provided is a method of manufacturing a voice coil, and more particularly, a method of manufacturing a voice coil in which a coil pattern is formed on a wafer level package. The method includes (a) forming a first coil pattern including a first area in which a first seed metal layer is exposed upward, a second area in which a first passivation layer for forming a via hole in the first area is formed, and a third area in which a first photoresist layer is formed in a portion of the first area and the second area on an upper surface of a wafer, (b) filling an inside of the via hole formed in the first coil pattern with a conductive material and forming first coil windings, and (c) removing the first photoresist layer formed in the third area.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 14, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jai Kyoung Choi, Eun Dong Kim, Hyun Hak Jung, Hyeong Min Kim, Jong Hwi Jung, Su Kyung Lim
  • Patent number: 9935072
    Abstract: The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: April 3, 2018
    Assignee: SFA SEMICON CO., LTD.
    Inventors: Byeong Ho Jeong, Eun Dong Kim, Jong Won Lee, Hyun Hak Jung, Jai Kyoung Choi
  • Patent number: 9905436
    Abstract: A method for manufacturing a wafer level fan-out package includes attaching a semiconductor chip on a partial area of an IO pattern formed on one surface of a wafer, forming a first passivation layer on surfaces of the semiconductor chip and the wafer, forming an RDL (redistribution layer) that is electrically conducted with the IO pattern and the semiconductor chip, in a partial area of a top surface of the first passivation layer, and forming a second passivation layer on the top surface of the first passivation layer and a partial surface of the RDL.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 27, 2018
    Assignee: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
    Inventors: You Jin Oh, Eun Dong Kim, Jong Won Lee, Jai Kyoung Choi
  • Patent number: 9905551
    Abstract: Provided is a method of manufacturing a wafer level package. The method includes forming a repassivation layer that encapsulates a plurality of semiconductor chips isolated from a wafer, forming a through encapsulation via (TEV) in the repassivation layer, forming a redistribution layer electrically connected to the TEV, and forming a bump ball on the redistribution layer.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: February 27, 2018
    Assignee: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
    Inventors: Eun Dong Kim, Jong Won Lee, Jai Kyoung Choi
  • Publication number: 20170125369
    Abstract: The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.
    Type: Application
    Filed: October 11, 2016
    Publication date: May 4, 2017
    Inventors: Byeong Ho JEONG, Eun Dong KIM, Jong Won LEE, Hyun Hak JUNG, Jai Kyoung CHOI
  • Publication number: 20170092510
    Abstract: A method for manufacturing a wafer level fan-out package includes attaching a semiconductor chip on a partial area of an IO pattern formed on one surface of a wafer, forming a first passivation layer on surfaces of the semiconductor chip and the wafer, forming an RDL (redistribution layer) that is electrically conducted with the IO pattern and the semiconductor chip, in a partial area of a top surface of the first passivation layer, and forming a second passivation layer on the top surface of the first passivation layer and a partial surface of the RDL.
    Type: Application
    Filed: February 25, 2016
    Publication date: March 30, 2017
    Inventors: You Jin OH, Eun Dong KIM, Jong Won LEE, Jai Kyoung CHOI
  • Publication number: 20170062368
    Abstract: Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a semiconductor die to the frame with respect to the fiducial mark pattern, encapsulating the semiconductor die with a passivation layer, for reconstituting the semiconductor die as a wafer level, and sequentially forming a metal seed layer, a redistribution layer, an under bump metal (UBM) seed layer, an UBM layer, and a solder ball on a bonding pad of the semiconductor die upward exposed by an opening region of the passivation layer to finish a fan-out type wafer level package.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 2, 2017
    Inventors: Hyun Hak JUNG, Eun Dong KIM, Jong Won LEE, Jai Kyoung CHOI, Byeong Ho JEONG
  • Publication number: 20170047831
    Abstract: Provided is a method of manufacturing a voice coil, and more particularly, a method of manufacturing a voice coil in which a coil pattern is formed on a wafer level package. The method includes (a) forming a first coil pattern including a first area in which a first seed metal layer is exposed upward, a second area in which a first passivation layer for forming a via hole in the first area is formed, and a third area in which a first photoresist layer is formed in a portion of the first area and the second area on an upper surface of a wafer, (b) filling an inside of the via hole formed in the first coil pattern with a conductive material and forming first coil windings, and (c) removing the first photoresist layer formed in the third area.
    Type: Application
    Filed: November 13, 2015
    Publication date: February 16, 2017
    Applicant: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
    Inventors: Jai Kyoung CHOI, Eun Dong KIM, Hyun Hak JUNG, Hyeong Min KIM, Jong Hwi JUNG, Su Kyung LIM
  • Publication number: 20160365195
    Abstract: Provided is a method for manufacturing a voice coil, and more particularly, to a voice coil manufacturing method for forming a coil pattern on a wafer level package. The method for manufacturing a voice coil includes forming a first passivation layer on an upper surface of a wafer, forming a first coil directly on the first passivation layer, forming a second passivation layer on the first passivation layer and on an upper surface of the first coil, forming a third passivation layer on an upper surface of the second passivation layer, forming a second coil directly on the third passivation layer, and forming an external connection terminal on a portion of the second coil.
    Type: Application
    Filed: July 9, 2015
    Publication date: December 15, 2016
    Inventors: Jai Kyoung CHOI, Eun Dong KIM, Hyun Hak JUNG, Hyeong Min KIM, Su Kyung LIM
  • Publication number: 20160365324
    Abstract: Provided is a method of manufacturing a wafer level package. The method includes forming a repassivation layer that encapsulates a plurality of semiconductor chips isolated from a wafer, forming a through encapsulation via (TEV) in the repassivation layer, forming a redistribution layer electrically connected to the TEV, and forming a bump ball on the redistribution layer.
    Type: Application
    Filed: July 15, 2015
    Publication date: December 15, 2016
    Inventors: Eun Dong KIM, Jong Won LEE, Jai Kyoung CHOI
  • Patent number: 9466586
    Abstract: Provided are a semiconductor package and a method for manufacturing a semiconductor package. The method for manufacturing a wafer-level fan-out package includes attaching semiconductor chips sawed to have a predetermined size to one surface of a wafer at predetermined intervals, forming a first passivation layer on surfaces of the semiconductor chips and the wafer, forming a redistribution layer electrically connected to the semiconductor chips on portions of an upper surface of the first passivation layer, forming a second passivation layer on the upper surface of the first passivation layer and surfaces of portions of the redistribution layer, forming external connection terminals on portions of the redistribution layer in which the second passivation layer has not been formed, and performing sawing along package boundary lines (sawing lines) and polishing the wafer to be removed such that lower surfaces of the semiconductor chips are exposed.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: October 11, 2016
    Assignee: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
    Inventors: Jai Kyoung Choi, Eun Dong Kim, Hyun Hak Jung, Hyeong Min Kim, Su Kyung Lim
  • Publication number: 20140301567
    Abstract: The present invention relates to a method of providing a compensation service for characteristics of a sound system using a smart device comprises: (1) receiving information of the sound system from the smart device; (2) retrieving the inputted sound characteristics of the sound system; and (3) transmitting a compensation signal according to the sound characteristics to the smart device. A user can be provided with a sound compensation service according to the sound characteristics of his/her sound system, i.e. a speaker, an earphone or a headphone, just by allowing a service providing server to receiving information about the sound system from the smart device, retrieving the sound characteristics, and then transmitting a compensation signal according to the sound characteristics to the smart device.
    Type: Application
    Filed: September 20, 2012
    Publication date: October 9, 2014
    Inventor: Eun Dong Kim