Patents by Inventor Eunho JUNG

Eunho JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230326784
    Abstract: An exposure apparatus includes a stage on which a target substrate is loaded and in which a plurality of holes are defined, a light source part radiating light to the stage, and a plurality of support pins disposed to penetrate the plurality of holes and supporting the target substrate, the plurality of support pins include a fixed support pin whose position is fixed in a plan view and a first variable support pin capable of reciprocating movement in a first direction, and the plurality of holes include a pair of first holes penetrated by the fixed support pin and arranged side by side at a predetermined interval along the first direction and a second hole penetrated by the first variable support pin and disposed between the pair of first holes.
    Type: Application
    Filed: April 11, 2023
    Publication date: October 12, 2023
    Inventors: SEUNG-WAN KIM, EUNHO JUNG, JAECHEOL LEE, DONGWON HAN
  • Patent number: 9651431
    Abstract: A semiconductor package includes a first package including a first substrate and a first semiconductor chip mounted on the first substrate and a second package facing and spaced apart from the first package. The second package includes a second substrate on which a second semiconductor chip is mounted. The semiconductor package also includes a connection structure electrically connecting the first and second packages to each other, a first temperature sensor connected to the first substrate, a second temperature sensor connected to the first semiconductor chip, and a third temperature sensor connected to the second semiconductor chip.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Choon Kim, Jichul Kim, Jin-Kwon Bae, Eunho Jung
  • Publication number: 20140247859
    Abstract: A semiconductor package includes a first package including a first substrate and a first semiconductor chip mounted on the first substrate and a second package facing and spaced apart from the first package. The second package includes a second substrate on which a second semiconductor chip is mounted. The semiconductor package also includes a connection structure electrically connecting the first and second packages to each other, a first temperature sensor connected to the first substrate, a second temperature sensor connected to the first semiconductor chip, and a third temperature sensor connected to the second semiconductor chip.
    Type: Application
    Filed: December 20, 2013
    Publication date: September 4, 2014
    Inventors: Jae Choon KIM, Jichul KIM, Jin-Kwon BAE, Eunho JUNG
  • Publication number: 20140239434
    Abstract: According to example embodiments, a semiconductor package may include a first package substrate, a first semiconductor chip on the first package substrate, and a thermistor array film on the first semiconductor chip. The thermistor array film may include a variable resistive film that covers the first semiconductor chip, and an array of electrode patterns that are connected to the variable resistive film. The array of electrode patterns may be connected to at least one of the upper and lower surfaces of the variable resistive film.
    Type: Application
    Filed: December 19, 2013
    Publication date: August 28, 2014
    Inventors: Jae Choon KIM, Jin-Kwon BAE, Eunho JUNG