Abstract: A composition for inhibiting proliferation of tumor comprising Rubus coreanus extract as effective component. It was found that the Rubus coreanus extract binds to PD-L1 present on the surface of cancer cells, thus blocking the interaction between cancer cells and PD-1 on the surface of T cells to activate T cells and exhibit an inhibitory effect on tumor proliferation, and it was also found that the Rubus coreanus extract shows an excellent anti-tumor immune activity in humanized PD-1 animal model induced with MC38 colorectal cancer expressing human PD-L1 and also a synergistic effect when co-administered with anti-cancer agents.

Abstract: The present invention pertains to a liquid electrolyte for lithium secondary batteries comprising: a) at least one fluorinated acyclic diether represented by the formula (I) R1—O—R2—O—R3, wherein R1 and R3 represent a fluorinated straight-chain alkyl group respectively: R2 represents an optionally fluorinated straight-chain alkylene group; and the sum of carbon atoms in R1, R2, and R3 is from 5 to 8, and preferably 6; b) at least one fluorinated acyclic carboxylic acid ester represented by the formula (II) R4—C(O)O—R5, wherein R4 and R5 represent an alkyl group respectively; the sum of carbon atoms of R4 and R5 is from 2 to 7; and at least one hydrogen in R5 is replaced by fluorine; c) at least one organic carbonate; and d) at least one lithium salt. The present invention also relates to a lithium secondary battery comprising an anode, a cathode, a separator and a liquid electrolyte according to the present invention.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform the program operation on the selected memory cells by using a first program voltage determined based on a first step voltage during a first program period and controls the peripheral circuit to perform the program operation on the selected memory cells by using a second program voltage determined based on a second step voltage different from the first step voltage during a second program period after the first program period.

Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.

Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.

Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.

Abstract: The present invention relates to an enhancer for catechin uptake enhancer in enterocytes, wherein, by mixing a green tea extract containing catechin as an active ingredient, a Dendropanax morbifera extract, and an onion extract at a proper ratio, the stability in the digestive organ can be improved and, eventually, the catechin uptake in enterocytes can be enhanced.

Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.

Abstract: The present invention relates to an enhancer for catechin uptake enhancer in enterocytes, wherein, by mixing a green tea extract containing catechin as an active ingredient, a Dendropanax morbifera extract, and an onion extract at a proper ratio, the stability in the digestive organ can be improved and, eventually, the catechin uptake in enterocytes can be enhanced.

Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.

Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including dielectric layers and internal electrodes stacked between the dielectric layers; and a pair of external electrodes each fixed to first and second surfaces of the ceramic body, facing each other, and connected to the internal electrodes, wherein the ceramic body has a third surface facing a printed circuit board and each of the pair of external electrodes includes mounting parts extended onto the third surface and having a preset length by which they are mounted on the printed circuit board and wherein connection parts between the pair of external electrodes and the mounting parts have a convexly curved shape having a size equal to or smaller than a preset corner radius.

Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including dielectric layers and internal electrodes stacked between the dielectric layers; and a pair of external electrodes each fixed to first and second surfaces of the ceramic body, facing each other, and connected to the internal electrodes, wherein the ceramic body has a third surface facing a printed circuit board and each of the pair of external electrodes includes mounting parts extended onto the third surface and having a preset length by which they are mounted on the printed circuit board and wherein connection parts between the pair of external electrodes and the mounting parts have a convexly curved shape having a size equal to or smaller than a preset corner radius.

Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.

Abstract: In a transaction processing system for processing a plurality of transactions in parallel with respect to hierarchical data, a copy of the hierarchical data is produced at a time of starting each transaction, and whether a collision between a reading or writing access to be made by a first transaction with respect to a copy and a writing or reading access made by the second transaction with respect to a copy will occur or not is judged and a processing for avoiding the collision is carried out when it is judged that the collision will occur. When the first transaction is to be finished normally, a writing access made by the first transaction with respect to a copy of the hierarchical data for the first transaction is reflected on the hierarchical data, as well as on a copy for the second transaction if the second transaction is not finished yet.