Patents by Inventor Eun Hye Choi

Eun Hye Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210408300
    Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Inventors: Moon Seung YANG, Eun Hye CHOI, Seung Mo KANG, Yong Seung KIM, Jung Taek KIM, Min-Hee CHOI
  • Patent number: 11133421
    Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 28, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Seung Yang, Eun Hye Choi, Seung Mo Kang, Yong Seung Kim, Jung Taek Kim, Min-Hee Choi
  • Patent number: 10912809
    Abstract: The present invention relates to an enhancer for catechin uptake enhancer in enterocytes, wherein, by mixing a green tea extract containing catechin as an active ingredient, a Dendropanax morbifera extract, and an onion extract at a proper ratio, the stability in the digestive organ can be improved and, eventually, the catechin uptake in enterocytes can be enhanced.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 9, 2021
    Assignee: AMOREPACIFIC CORPORATION
    Inventors: Su Kyung Kim, Jin Oh Chung, Wan Gi Kim, Jeong Kee Kim, Song Seok Shin, Soon Mi Shim, Da Yeon Lee, Sang Ryun Yim, Eun Hye Choi
  • Publication number: 20200395489
    Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.
    Type: Application
    Filed: March 4, 2020
    Publication date: December 17, 2020
    Inventors: Moon Seung YANG, Eun Hye CHOI, Seung Mo KANG, Yong Seung KIM, Jung Taek KIM, Min-Hee CHOI
  • Publication number: 20200016224
    Abstract: The present invention relates to an enhancer for catechin uptake enhancer in enterocytes, wherein, by mixing a green tea extract containing catechin as an active ingredient, a Dendropanax morbifera extract, and an onion extract at a proper ratio, the stability in the digestive organ can be improved and, eventually, the catechin uptake in enterocytes can be enhanced.
    Type: Application
    Filed: November 21, 2017
    Publication date: January 16, 2020
    Applicant: AMOREPACIFIC CORPORATION
    Inventors: Su Kyung KIM, Jin Oh CHUNG, Wan Gi KIM, Jeong Kee KIM, Song Seok SHIN, Soon Mi SHIM, Da Yeon LEE, Sang Ryun YIM, Eun Hye CHOI
  • Patent number: 9818824
    Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Seung Yang, Eun Hye Choi, Sun Jung Kim, Seung Hun Lee, Hyun-Jung Lee
  • Publication number: 20160218181
    Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.
    Type: Application
    Filed: December 14, 2015
    Publication date: July 28, 2016
    Inventors: Moon Seung Yang, Eun Hye Choi, Sun Jung Kim, Seung Hun Lee, Hyun-Jung Lee
  • Patent number: 8614876
    Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including dielectric layers and internal electrodes stacked between the dielectric layers; and a pair of external electrodes each fixed to first and second surfaces of the ceramic body, facing each other, and connected to the internal electrodes, wherein the ceramic body has a third surface facing a printed circuit board and each of the pair of external electrodes includes mounting parts extended onto the third surface and having a preset length by which they are mounted on the printed circuit board and wherein connection parts between the pair of external electrodes and the mounting parts have a convexly curved shape having a size equal to or smaller than a preset corner radius.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: December 24, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hae Suk Chung, Dae Bok Oh, Eun Hye Choi, Eun Hyuk Chae, Kang Heon Hur
  • Patent number: 8451580
    Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 28, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hae Suk Chung, Byoung Hwa Lee, Eun Hyuk Chae, Eun Hye Choi, Kang Heon Hur, Dae Bok Oh
  • Publication number: 20120268860
    Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.
    Type: Application
    Filed: November 1, 2011
    Publication date: October 25, 2012
    Inventors: Hae Suk CHUNG, Byoung Hwa Lee, Eun Hyuk Chae, Eun Hye Choi, Kang Heon Hur, Dae Bok Oh
  • Publication number: 20120268859
    Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including dielectric layers and internal electrodes stacked between the dielectric layers; and a pair of external electrodes each fixed to first and second surfaces of the ceramic body, facing each other, and connected to the internal electrodes, wherein the ceramic body has a third surface facing a printed circuit board and each of the pair of external electrodes includes mounting parts extended onto the third surface and having a preset length by which they are mounted on the printed circuit board and wherein connection parts between the pair of external electrodes and the mounting parts have a convexly curved shape having a size equal to or smaller than a preset corner radius.
    Type: Application
    Filed: October 26, 2011
    Publication date: October 25, 2012
    Inventors: Hae Suk Chung, Dae Bok Oh, Eun Hye Choi, Eun Hyuk Chae, Kang Heon Hur
  • Publication number: 20040267747
    Abstract: In a transaction processing system for processing a plurality of transactions in parallel with respect to hierarchical data, a copy of the hierarchical data is produced at a time of starting each transaction, and whether a collision between a reading or writing access to be made by a first transaction with respect to a copy and a writing or reading access made by the second transaction with respect to a copy will occur or not is judged and a processing for avoiding the collision is carried out when it is judged that the collision will occur. When the first transaction is to be finished normally, a writing access made by the first transaction with respect to a copy of the hierarchical data for the first transaction is reflected on the hierarchical data, as well as on a copy for the second transaction if the second transaction is not finished yet.
    Type: Application
    Filed: January 28, 2004
    Publication date: December 30, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Eun Hye Choi, Tatsunori Kanai