Patents by Inventor Eun Hye Choi
Eun Hye Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240122017Abstract: A display apparatus includes a base substrate on which a display area and a non-display area are defined, a first via insulating layer on the base substrate, a first power supply wire in the non-display area on the first via insulating layer, a second power supply wire in the non-display area on the first via insulating layer spaced apart from the first power supply wire, a first dam on the base substrate, overlapping the first and second power supply wires, and extending along the non-display area, a first stacked structure on the first via insulating layer between the first dam and the display area, and having a height less than a height of the first dam, and an organic layer on the first stacked structure and the first dam to overlap a substantially entire portion of the first stacked structure and at least a portion of the first dam.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Ki Ho BANG, Eun Hye KIM, Won Suk CHOI
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Patent number: 11951130Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.Type: GrantFiled: March 1, 2021Date of Patent: April 9, 2024Assignee: Eutilex Co., Ltd.Inventors: Byoung S. Kwon, Young Ho Kim, Kwang Hee Kim, Ji Won Chung, Young Gyoon Chang, Bo Rim Yi, Jung Yun Lee, Seung Hyun Lee, Sun Woo Im, Jin Kyung Choi, Hyun Tae Son, Eun Hye Yoo
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Publication number: 20230298668Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform the program operation on the selected memory cells by using a first program voltage determined based on a first step voltage during a first program period and controls the peripheral circuit to perform the program operation on the selected memory cells by using a second program voltage determined based on a second step voltage different from the first step voltage during a second program period after the first program period.Type: ApplicationFiled: June 21, 2022Publication date: September 21, 2023Applicant: SK hynix Inc.Inventor: Eun Hye CHOI
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Patent number: 11569389Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.Type: GrantFiled: September 9, 2021Date of Patent: January 31, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Moon Seung Yang, Eun Hye Choi, Seung Mo Kang, Yong Seung Kim, Jung Taek Kim, Min-Hee Choi
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Publication number: 20210408300Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.Type: ApplicationFiled: September 9, 2021Publication date: December 30, 2021Inventors: Moon Seung YANG, Eun Hye CHOI, Seung Mo KANG, Yong Seung KIM, Jung Taek KIM, Min-Hee CHOI
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Patent number: 11133421Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.Type: GrantFiled: March 4, 2020Date of Patent: September 28, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Moon Seung Yang, Eun Hye Choi, Seung Mo Kang, Yong Seung Kim, Jung Taek Kim, Min-Hee Choi
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Patent number: 10912809Abstract: The present invention relates to an enhancer for catechin uptake enhancer in enterocytes, wherein, by mixing a green tea extract containing catechin as an active ingredient, a Dendropanax morbifera extract, and an onion extract at a proper ratio, the stability in the digestive organ can be improved and, eventually, the catechin uptake in enterocytes can be enhanced.Type: GrantFiled: November 21, 2017Date of Patent: February 9, 2021Assignee: AMOREPACIFIC CORPORATIONInventors: Su Kyung Kim, Jin Oh Chung, Wan Gi Kim, Jeong Kee Kim, Song Seok Shin, Soon Mi Shim, Da Yeon Lee, Sang Ryun Yim, Eun Hye Choi
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Publication number: 20200395489Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.Type: ApplicationFiled: March 4, 2020Publication date: December 17, 2020Inventors: Moon Seung YANG, Eun Hye CHOI, Seung Mo KANG, Yong Seung KIM, Jung Taek KIM, Min-Hee CHOI
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Publication number: 20200016224Abstract: The present invention relates to an enhancer for catechin uptake enhancer in enterocytes, wherein, by mixing a green tea extract containing catechin as an active ingredient, a Dendropanax morbifera extract, and an onion extract at a proper ratio, the stability in the digestive organ can be improved and, eventually, the catechin uptake in enterocytes can be enhanced.Type: ApplicationFiled: November 21, 2017Publication date: January 16, 2020Applicant: AMOREPACIFIC CORPORATIONInventors: Su Kyung KIM, Jin Oh CHUNG, Wan Gi KIM, Jeong Kee KIM, Song Seok SHIN, Soon Mi SHIM, Da Yeon LEE, Sang Ryun YIM, Eun Hye CHOI
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Patent number: 9818824Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.Type: GrantFiled: December 14, 2015Date of Patent: November 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Moon Seung Yang, Eun Hye Choi, Sun Jung Kim, Seung Hun Lee, Hyun-Jung Lee
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Publication number: 20160218181Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.Type: ApplicationFiled: December 14, 2015Publication date: July 28, 2016Inventors: Moon Seung Yang, Eun Hye Choi, Sun Jung Kim, Seung Hun Lee, Hyun-Jung Lee
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Patent number: 8614876Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including dielectric layers and internal electrodes stacked between the dielectric layers; and a pair of external electrodes each fixed to first and second surfaces of the ceramic body, facing each other, and connected to the internal electrodes, wherein the ceramic body has a third surface facing a printed circuit board and each of the pair of external electrodes includes mounting parts extended onto the third surface and having a preset length by which they are mounted on the printed circuit board and wherein connection parts between the pair of external electrodes and the mounting parts have a convexly curved shape having a size equal to or smaller than a preset corner radius.Type: GrantFiled: October 26, 2011Date of Patent: December 24, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hae Suk Chung, Dae Bok Oh, Eun Hye Choi, Eun Hyuk Chae, Kang Heon Hur
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Patent number: 8451580Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.Type: GrantFiled: November 1, 2011Date of Patent: May 28, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hae Suk Chung, Byoung Hwa Lee, Eun Hyuk Chae, Eun Hye Choi, Kang Heon Hur, Dae Bok Oh
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Publication number: 20120268860Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.Type: ApplicationFiled: November 1, 2011Publication date: October 25, 2012Inventors: Hae Suk CHUNG, Byoung Hwa Lee, Eun Hyuk Chae, Eun Hye Choi, Kang Heon Hur, Dae Bok Oh
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Publication number: 20120268859Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including dielectric layers and internal electrodes stacked between the dielectric layers; and a pair of external electrodes each fixed to first and second surfaces of the ceramic body, facing each other, and connected to the internal electrodes, wherein the ceramic body has a third surface facing a printed circuit board and each of the pair of external electrodes includes mounting parts extended onto the third surface and having a preset length by which they are mounted on the printed circuit board and wherein connection parts between the pair of external electrodes and the mounting parts have a convexly curved shape having a size equal to or smaller than a preset corner radius.Type: ApplicationFiled: October 26, 2011Publication date: October 25, 2012Inventors: Hae Suk Chung, Dae Bok Oh, Eun Hye Choi, Eun Hyuk Chae, Kang Heon Hur
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Publication number: 20040267747Abstract: In a transaction processing system for processing a plurality of transactions in parallel with respect to hierarchical data, a copy of the hierarchical data is produced at a time of starting each transaction, and whether a collision between a reading or writing access to be made by a first transaction with respect to a copy and a writing or reading access made by the second transaction with respect to a copy will occur or not is judged and a processing for avoiding the collision is carried out when it is judged that the collision will occur. When the first transaction is to be finished normally, a writing access made by the first transaction with respect to a copy of the hierarchical data for the first transaction is reflected on the hierarchical data, as well as on a copy for the second transaction if the second transaction is not finished yet.Type: ApplicationFiled: January 28, 2004Publication date: December 30, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Eun Hye Choi, Tatsunori Kanai