Patents by Inventor Eun Hye Do
Eun Hye Do has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230253371Abstract: A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.Type: ApplicationFiled: April 20, 2023Publication date: August 10, 2023Applicant: SK hynix Inc.Inventors: Eun Hye DO, Jong Hoon KIM
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Patent number: 11664351Abstract: A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.Type: GrantFiled: January 25, 2021Date of Patent: May 30, 2023Assignee: SK hynix Inc.Inventors: Eun Hye Do, Jong Hoon Kim
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Publication number: 20220059504Abstract: A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.Type: ApplicationFiled: January 25, 2021Publication date: February 24, 2022Applicant: SK hynix Inc.Inventors: Eun Hye DO, Jong Hoon KIM
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Patent number: 10903189Abstract: A stack package includes a second semiconductor die stacked on the first semiconductor die, a third semiconductor die disposed on the lifting supporter. The third semiconductor die vertically and partially overlapping with the second semiconductor die.Type: GrantFiled: December 21, 2018Date of Patent: January 26, 2021Assignee: SK hynix Inc.Inventor: Eun Hye Do
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Publication number: 20200091112Abstract: A stack package includes a second semiconductor die stacked on the first semiconductor die, a third semiconductor die disposed on the lifting supporter. The third semiconductor die vertically and partially overlapping with the second semiconductor die.Type: ApplicationFiled: December 21, 2018Publication date: March 19, 2020Applicant: SK hynix Inc.Inventor: Eun Hye DO
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Patent number: 9679865Abstract: A semiconductor package includes a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode.Type: GrantFiled: April 15, 2014Date of Patent: June 13, 2017Assignee: SK hynix Inc.Inventor: Eun Hye Do
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Patent number: 9305912Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: GrantFiled: June 9, 2015Date of Patent: April 5, 2016Assignee: SK Hynix Inc.Inventors: Hee Min Shin, Cheol Ho Joh, Eun Hye Do, Ji Eun Kim, Kyu Won Lee
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Publication number: 20150270252Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: ApplicationFiled: June 9, 2015Publication date: September 24, 2015Inventors: Hee Min SHIN, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Kyu Won LEE
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Patent number: 9082634Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: GrantFiled: December 29, 2010Date of Patent: July 14, 2015Assignee: SK Hynix Inc.Inventors: Hee-Min Shin, Cheol-Ho Joh, Eun-Hye Do, Ji-Eun Kim, Kyu-Won Lee
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Publication number: 20150131255Abstract: A semiconductor package may include: a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode.Type: ApplicationFiled: April 15, 2014Publication date: May 14, 2015Applicant: SK hynix Inc.Inventor: Eun Hye DO
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Patent number: 8564141Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.Type: GrantFiled: March 2, 2011Date of Patent: October 22, 2013Assignee: SK Hynix Inc.Inventors: Kyu Won Lee, Cheol Ho Joh, Eun Hye Do, Ji Eun Kim, Hee Min Shin
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Publication number: 20130256887Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.Type: ApplicationFiled: May 30, 2013Publication date: October 3, 2013Applicant: SK hynix Inc.Inventors: Kyu Won LEE, Cheol Ho JOH, Eun-Hye DO, Ji Eun KIM, Hee Min SHIN
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Patent number: 8476751Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.Type: GrantFiled: April 28, 2011Date of Patent: July 2, 2013Assignee: SK Hynix Inc.Inventors: Kyu Won Lee, Cheol Ho Joh, Eun-Hye Do, Ji Eun Kim, Hee Min Shin
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Publication number: 20120018879Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: ApplicationFiled: December 29, 2010Publication date: January 26, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hee-Min SHIN, Cheol-Ho JOH, Eun-Hye DO, Ji-Eun KIM, Kyu-Won LEE
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Publication number: 20110272798Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.Type: ApplicationFiled: March 2, 2011Publication date: November 10, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyu Won LEE, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Hee Min SHIN
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Publication number: 20110272820Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.Type: ApplicationFiled: April 28, 2011Publication date: November 10, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyu Won LEE, Cheol Ho JOH, Eun-Hye DO, Ji Eun KIM, Hee Min SHIN
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WAFER MOUNT TAPE, WAFER PROCESSING APPARATUS AND METHOD OF USING THE SAME FOR USE IN THINNING WAFERS
Publication number: 20110189928Abstract: A wafer mount tape, a wafer processing apparatus and an associated method of using the wafer mount tape for use in wafer thinning operations is presented. The wafer mount tape includes a tape body, a first adhesive member and a second adhesive member. The tape body has a first region, a second region and a third region. The first region of the tape body is for being disposed onto a wafer. The second region of the tape body is defined along a periphery of the first region. The third region of the tape body is defined along a periphery of the second region. The first adhesive is member is disposed at the first region. The second adhesive member is disposed at the third region.Type: ApplicationFiled: March 17, 2011Publication date: August 4, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hee Min SHIN, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Kyu Won LEE -
Patent number: 7859108Abstract: A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.Type: GrantFiled: December 27, 2007Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventors: Woong Sun Lee, Il Hwan Cho, Myung Geun Park, Cheol Ho Joh, Eun Hye Do, Ki Young Kim, Ji Eun Kim, Jong Hyun Nam
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WAFER MOUNT TAPE, WAFER PROCESSING APPARATUS AND METHOD OF USING THE SAME FOR USE IN THINNING WAFERS
Publication number: 20100092718Abstract: A wafer mount tape, a wafer processing apparatus and an associated method of using the wafer mount tape for use in wafer thinning operations is presented. The wafer mount tape includes a tape body, a first adhesive member and a second adhesive member. The tape body has a first region, a second region and a third region. The first region of the tape body is for being disposed onto a wafer. The second region of the tape body is defined along a periphery of the first region. The third region of the tape body is defined along a periphery of the second region. The first adhesive member is disposed at the first region. The second adhesive member is disposed at the third region.Type: ApplicationFiled: December 30, 2008Publication date: April 15, 2010Inventors: Hee Min SHIN, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Kyu Won LEE -
Publication number: 20090140426Abstract: A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.Type: ApplicationFiled: December 27, 2007Publication date: June 4, 2009Inventors: Woong Sun LEE, Il Hwan CHO, Myung Geun PARK, Cheol Ho JOH, Eun Hye DO, Ki Young KIM, Ji Eun KIM, Jong Hyun NAM