Abstract: A server according to an embodiment includes a processor configured to receive a friend add request for a target account from a user terminal accessed with a user account; based on one of the user account and the target account being a protected account, transmit an approval request for the friend add request to a protector account connected to the protected account; and based on receiving a reply to the approval request from the protector terminal, add the target account to a friend list of the user account.

Abstract: Provided is a display device. The display device includes a display panel which includes a base substrate, a thin-film transistor layer on the base substrate, and a light emitting element layer comprising light emitting elements on the thin-film transistor layer; a cover window on the light emitting element layer of the display panel; and a fingerprint recognition sensor layer under the display panel. The base substrate includes a first base, a second base on the first base, and a light blocking layer between the first base and the second base, and the light blocking layer includes holes through which light reflected by a finger touching the cover window passes.

Abstract: A quantization device includes: a trellis-structured vector quantizer which quantizes a first error vector between an N-dimensional (here, “N” is two or more) subvector and a first predictive vector; and an inter-frame predictor which generates a first predictive vector from the quantized N-dimensional subvector, wherein the inter-frame predictor uses a predictive coefficient comprising an N×N matrix and performs an inter-frame prediction using the quantized N-dimensional subvector of a previous stage.

Abstract: Compositions and methods are described for alleviating, preventing, or treating adverse effects of cholinesterase inhibitors by administering an effective amount of an antioxidant to a subject in need thereof. Composition and methods are described for preventing or treating a brain disease by administering a cholinesterase inhibitor and an antioxidant to a subject in need thereof.

Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.

Abstract: A display device includes a light blocking layer positioned on a substrate and including a first portion and a second portion having a thickness greater than a thickness of the first portion; a buffer layer positioned above the light blocking layer; a semiconductor layer positioned over the buffer layer and including a source region, a channel region, and a drain region; a gate insulating layer positioned over the semiconductor layer; a gate electrode positioned over the gate insulating layer; an interlayer insulating layer positioned over the gate electrode, and including a first opening overlapping the second portion of the light blocking layer in a plan view and a second opening overlapping the source region of the semiconductor layer in a plan view; and a dummy gate electrode positioned on a side surface of the first opening.

Abstract: A display device includes insulating layers, a light-emitting element, and a pixel circuit electrically connected to the light-emitting element. The pixel circuit includes a first transistor. The first transistor includes a metal oxide semiconductor pattern including a source region, a drain region and a channel region disposed between the source region and the drain region, a first gate disposed on the metal oxide semiconductor pattern and overlapping the channel region in a plan view, and a metal oxide pattern disposed on the first gate.

Abstract: A display device includes a substrate, a corrosion prevention layer on the substrate and including an inorganic material, a first conductive layer on the corrosion prevention layer and including aluminum or an aluminum alloy, a first insulating film on the first conductive layer, a semiconductor layer on the first insulating film and including a channel region of a transistor, a second insulating film on the semiconductor layer, and a second conductive layer on the second insulating film and including a barrier layer, which includes titanium, and a main conductive layer, which includes aluminum or an aluminum alloy, wherein the semiconductor layer includes an oxide semiconductor, and the barrier layer is between the semiconductor layer and the main conductive layer and overlaps the channel region of the transistor.

Abstract: A display device includes a substrate, a corrosion prevention layer on the substrate and including an inorganic material, a first conductive layer on the corrosion prevention layer and including aluminum or an aluminum alloy, a first insulating film on the first conductive layer, a semiconductor layer on the first insulating film and including a channel region of a transistor, a second insulating film on the semiconductor layer, and a second conductive layer on the second insulating film and including a barrier layer, which includes titanium, and a main conductive layer, which includes aluminum or an aluminum alloy, wherein the semiconductor layer includes an oxide semiconductor, and the barrier layer is between the semiconductor layer and the main conductive layer and overlaps the channel region of the transistor.

Abstract: A display device according to an embodiment includes: a first metal layer disposed on a substrate; a first insulating layer disposed on the first metal layer; a first transistor disposed on the first insulating layer and including a semiconductor layer; and a light-emitting device electrically connected to the first transistor, wherein the first metal layer includes a first portion with a first thickness and a second portion with a second thickness, the second thickness is greater than the first thickness, and the semiconductor layer is electrically connected to the first metal layer.

Abstract: A display device includes a display area and a functional area defining a through-portion therein. At least a portion of the functional area is surrounded by the display area. The display device includes an insulation layer disposed on a base substrate and defining a disconnection portion in the functional area, a pixel array disposed on the base substrate in the display area, and a mask pattern including a metal oxide and extending along the disconnection portion in a plan view.

Abstract: A display device includes a substrate, a corrosion prevention layer on the substrate and including an inorganic material, a first conductive layer on the corrosion prevention layer and including aluminum or an aluminum alloy, a first insulating film on the first conductive layer, a semiconductor layer on the first insulating film and including a channel region of a transistor, a second insulating film on the semiconductor layer, and a second conductive layer on the second insulating film and including a barrier layer, which includes titanium, and a main conductive layer, which includes aluminum or an aluminum alloy, wherein the semiconductor layer includes an oxide semiconductor, and the barrier layer is between the semiconductor layer and the main conductive layer and overlaps the channel region of the transistor.

Abstract: A display device according to some embodiments includes: a substrate; a first transistor and a second transistor disposed on the substrate and spaced apart from each other; a first electrode connected to one of the first transistor and the second transistor; a second electrode overlapping the first electrode; and a light emitting layer between the first electrode and the second electrode, wherein the first transistor may include: a first semiconductor layer on the substrate; a first gate electrode on the first semiconductor layer; and a first source electrode and a first drain electrode connected to the first semiconductor layer, and the second transistor may include: a second semiconductor layer on the substrate; a second gate electrode on the second semiconductor layer; and a second source electrode and a second drain electrode connected to the second semiconductor layer, and the first gate electrode and the second semiconductor layer may be on the same layer.

Abstract: A semiconductor device may include a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the substrate to cover the gate electrode, an active layer including an oxide semiconductor disposed on the gate insulation layer, an insulating interlayer disposed on the gate insulation layer to cover the active layer, a protection structure including a plurality of metal oxide layers disposed on the insulating interlayer, and a source electrode and a drain electrode disposed on the protection structure.

Abstract: A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A.

Abstract: A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A.

Abstract: A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, the semiconductor layer overlapping at least a portion of the gate electrode, a plurality of etch stoppers on the semiconductor layer, and a source electrode and a drain electrode spaced apart from each other and disposed on the etch stoppers and the semiconductor layer, wherein a plurality of channel regions are defined in the semiconductor layer by the etch stoppers on the semiconductor layer.

Abstract: A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes a substrate and a gate electrode disposed on the substrate. A gate insulating layer is disposed on the substrate and covers the gate electrode. A semiconductor layer is disposed on the gate insulating layer and includes a channel region, a source region, and a drain region. The source and drain regions are separated from each other by the channel region. An etch stopper is disposed on the semiconductor layer. A passivation layer is disposed on the semiconductor layer and covers the etch stopper. A source electrode and a drain electrode are disposed on the passivation layer and are respectively connected to the source region and the drain region. The passivation layer includes a first sub-passivation layer including aluminum oxide (AlOx).

Abstract: An organic light-emitting display is disclosed. In one embodiment, the display includes i) a substrate, ii) a thin film transistor formed on the substrate, and comprising i) a gate electrode, ii) an active layer electrically insulated from the gate electrode, and iii) source and drain electrodes that are electrically connected to the active layer and iii) a first electrode electrically connected to the thin film transistor. The display further includes an intermediate layer formed on the first electrode and comprising an organic emission layer and a second electrode formed on the intermediate layer, wherein the source electrode or the drain electrode has an optical blocking portion extending in the direction of substrate thickness.