Abstract: A storage device may transmit a command set to a memory, set a plurality of flag bits based on transmission status of a plurality of commands included in the command set, respectively, and determine whether an error occurred in the process of transmitting the command set to the memory based on the plurality of flag bits. Each of the plurality of flag bits has a first value or a second value, and the command set includes a reset command, a command set start command, and a command set end command.

Abstract: A storage device may determine first priority parameters and second priority parameters for a plurality of memory dies on the basis of temperatures of the plurality of memory dies measured at a first time point and a second time point. The storage device may determine priorities of the plurality of memory dies for a read operation or a write operation on the basis of the first priority parameters and the second priority parameters for the plurality of memory dies.

Abstract: An electronic device includes a communication interface for, when a predetermined event occurs, transmitting a data signal generated based on data and a signal processing characteristic value to a memory system, and receiving eye diagram information corresponding to the data signal from the memory system; and a signal processing controller for controlling the signal processing characteristic value, based on an interval change value of the eye diagram information.

Abstract: A method for operating an electronic device includes predicting a temperature rise of the electronic device when the application is started, predicting a temperature of the electronic device based on the predicted temperature rise and a current temperature of the electronic device, and lowering the temperature of the electronic device when the predicted temperature of the electronic device is higher than a preset threshold temperature.

Abstract: A storage device may determine first priority parameters and second priority parameters for a plurality of memory dies on the basis of temperatures of the plurality of memory dies measured at a first time point and a second time point. The storage device may determine priorities of the plurality of memory dies for a read operation or a write operation on the basis of the first priority parameters and the second priority parameters for the plurality of memory dies.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including a plurality of memory blocks, the memory device being configured to output voltage information indicating whether an unstable state of an input voltage has occurred, the input voltage being provided to the memory device from an external power source, and a memory controller configured to store a read count indicating a number of times that one or more read operations are performed on each of the plurality of memory blocks and to control the memory device to move data stored in a first memory block for which the read count exceeds a threshold count to a second memory block, and configured to adjust the threshold count based on the voltage information.

Abstract: A memory system and a memory controller are disclosed. By determining whether an error has occurred in target data stored in a predetermined target memory area of the memory device and determining, in response to whether an error has occurred in the target data, the magnitude of the supplied power based on a first operation parameter selected among predetermined candidate operation parameters in connection with the magnitude of the supplied power, the memory controller may stably drive a firmware, and may handle an operation error of the firmware due to a change in external environment.

Abstract: A data storage apparatus may include a storage and a controller. The storage includes a plurality of planes each composed of a plurality of memory blocks, and is divided into a first region and a second region. An original of system data and a copy of the system data are stored in the first region. The controller is configured to perform a relief operation of moving the copy of the system data stored in a source memory block of the first region to a victim plane and switching the source memory block to a region replaceable with the second region.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including a plurality of memory blocks, the memory device being configured to output voltage information indicating whether an unstable state of an input voltage has occurred, the input voltage being provided to the memory device from an external power source, and a memory controller configured to store a read count indicating a number of times that one or more read operations are performed on each of the plurality of memory blocks and to control the memory device to move data stored in a first memory block for which the read count exceeds a threshold count to a second memory block, and configured to adjust the threshold count based on the voltage information.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device and a memory controller. The memory device may include first memory blocks and second memory blocks. The memory controller may be configured to control the memory device so that valid data stored in a victim block, among the first memory blocks, is stored in a target block, among the second memory blocks, based on a result of a comparison between an amount of valid data stored in the victim block and a reference value. Each of the first memory blocks may include memory cells each configured to store n bits, where n is a natural number of 2 or more. Each of the second memory blocks may include memory cells each configured to store m bits, where m is a natural number less than n.

Abstract: A storage device may include a memory device and a memory controller. The memory device may include a memory block including a plurality of pages. When a sudden power off is detected in which power supplied to the memory device is abnormally interrupted during a normal program operation on one page among the plurality of pages, the memory controller may control the memory device to perform a dummy program operation on a selected page among the plurality of pages after the sudden power-off. The memory controller may control the memory device to perform the normal program operation and the dummy program operation by using an Incremental Step Pulse Program (ISPP) method. The memory controller may control the memory device to perform the dummy program operation in a smaller number of program loops as compared with the normal program operation.

Abstract: A data storage apparatus may include a storage including a storage including a plurality of planes each composed of a plurality of memory blocks, each of the plurality of planes being divided into a first region where an original of system data and a copy of the system data are stored and a second region where user data is stored; and a controller configured to control an operation of the storage and to perform a relief operation of moving the copy of the system data stored in a source memory block of the first region to the second region of a victim plane and switching the source memory block to a region replaceable with the second region.

Abstract: A storage device may include a memory device and a memory controller. The memory device may include a memory block including a plurality of pages. When a sudden power off is detected in which power supplied to the memory device is abnormally interrupted during a normal program operation on one page among the plurality of pages, the memory controller may control the memory device to perform a dummy program operation on a selected page among the plurality of pages after the sudden power-off. The memory controller may control the memory device to perform the normal program operation and the dummy program operation by using an Incremental Step Pulse Program (ISPP) method. The memory controller may control the memory device to perform the dummy program operation in a smaller number of program loops as compared with the normal program operation.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device and a memory controller. The memory device may include first memory blocks and second memory blocks. The memory controller may be configured to control the memory device so that valid data stored in a victim block, among the first memory blocks, is stored in a target block, among the second memory blocks, based on a result of a comparison between an amount of valid data stored in the victim block and a reference value. Each of the first memory blocks may include memory cells each configured to store n bits, where n is a natural number of 2 or more. Each of the second memory blocks may include memory cells each configured to store m bits, where m is a natural number less than n.

Abstract: A memory system and a memory controller are disclosed. By determining whether an error has occurred in target data stored in a predetermined target memory area of the memory device and determining, in response to whether an error has occurred in the target data, the magnitude of the supplied power based on a first operation parameter selected among predetermined candidate operation parameters in connection with the magnitude of the supplied power, the memory controller may stably drive a firmware, and may handle an operation error of the firmware due to a change in external environment.

Abstract: Provided is an operation method of a controller which controls a memory device including an operation parameter register. The operation method may include: receiving a write request from a host, the write request including a write command, a write address and write data; extracting from the write data a parameter change internal command for changing an operation parameter value of the memory device based on whether the write address is a specific address, the extracted parameter change internal command including an operation parameter address and operation parameter data; and setting an operation parameter of the memory device by controlling the memory device to store the operation parameter data in the operation parameter register corresponding to the operation parameter address, the operation parameter data corresponding to the operation parameter value.