Patents by Inventor Eun Jeong KWAK

Eun Jeong KWAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Variable resistive memory device
    Patent number: 10546893
    Abstract: A variable resistive memory device may include a semiconductor substrate, a device layer, an upper metal interconnect, a plurality of memory cells, and an uppermost metal interconnect. The device layer may be formed on the semiconductor substrate including memory cell array regions, and may include a plurality of lower metal interconnect layers. The upper metal interconnect may be arranged on the device layer, and may include a plurality of metal patterns. The plurality of memory may be arranged over the device layer in which the upper metal interconnect is formed and are in contact with certain metal patterns selected from the metal patterns constituting the upper metal interconnect. The uppermost metal interconnect may be located over the plurality of memory cells, and may be in contact with other portion of the metal patterns constituting the upper metal interconnect.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Young Hee Yoon, Eun Jeong Kwak
  • VARIABLE RESISTIVE MEMORY DEVICE
    Publication number: 20180061891
    Abstract: A variable resistive memory device may include a semiconductor substrate, a device layer, an upper metal interconnect, a plurality of memory cells, and an uppermost metal interconnect. The device layer may be formed on the semiconductor substrate including memory cell array regions, and may include a plurality of lower metal interconnect layers. The upper metal interconnect may be arranged on the device layer, and may include a plurality of metal patterns. The plurality of memory may be arranged over the device layer in which the upper metal interconnect is formed and are in contact with certain metal patterns selected from the metal patterns constituting the upper metal interconnect. The uppermost metal interconnect may be located over the plurality of memory cells, and may be in contact with other portion of the metal patterns constituting the upper metal interconnect.
    Type: Application
    Filed: April 20, 2017
    Publication date: March 1, 2018
    Applicant: SK hynix Inc.
    Inventors: Young Hee YOON, Eun Jeong KWAK