Abstract: A data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block a remaining signal path among a plurality of signal paths for transmitting data except for a signal path corresponding to a currently selected driving strength. The pre-driver may be configured to drive data, which are transmitted through the signal path corresponding to the currently selected driving strength, using an impedance determined in accordance with a plurality of impedance control codes.

Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

Abstract: A buffer circuit includes a first buffer configured to operate at an external power voltage, generate first and second buffer signals by comparing an input signal with a reference voltage, and control potential levels of the first and second buffer signals in response to a common mode feedback voltage; a second buffer configured to operate at an internal power voltage and generate an output signal in response to the first and second buffer signals; and a replica circuit configured to generate the common mode feedback voltage to be less than the internal power voltage.

Abstract: A buffer circuit includes a first buffer configured to operate at an external power voltage, generate first and second buffer signals by comparing an input signal with a reference voltage, and control potential levels of the first and second buffer signals in response to a common mode feedback voltage; a second buffer configured to operate at an internal power voltage and generate an output signal in response to the first and second buffer signals; and a replica circuit configured to generate the common mode feedback voltage to be less than the internal power voltage.

Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.

Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.

Abstract: A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.

Abstract: An analog to digital converter includes a first DAC unit configured to vary a level of a reference voltage output through a first node according to a first code, a second DAC unit coupled in parallel to the first DAC unit on the basis of the first node and configured to vary the level of the reference voltage according to a second code, a comparator configured to generate a comparison result signal by comparing an input voltage and the reference voltage, and at least one register array configured to store the first code and the second code with initial values and store the first code and the second code by varying values of the first code and the second code according to the comparison result signal.

Abstract: A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The data latch circuit may output latched data to an input/output line in response to a cell select signal. The data first stage amplification circuit may generate driving data to a voltage level of an external power supply voltage in response to a voltage level of the input/output line. The data first stage amplification circuit may precharge the input/output line to a voltage level lower than the external power supply voltage and higher than a ground voltage in response to a precharge signal.

Abstract: A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.

Abstract: A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The data latch circuit may output latched data to an input/output line in response to a cell select signal. The data first stage amplification circuit may generate driving data to a voltage level of an external power supply voltage in response to a voltage level of the input/output line. The data first stage amplification circuit may precharge the input/output line to a voltage level lower than the external power supply voltage and higher than a ground voltage in response to a precharge signal.

Abstract: A method of detecting camera tempering and a system therefor are provided. The method includes: performing at least one of following operations: (i) detecting a size of a foreground in an image, and determining whether a first condition, that the size exceeds a first reference value, is satisfied, (ii) detecting change of a sum of the largest pixel value differences among pixel value differences between adjacent pixels in selected horizontal lines of the image, according to time, and determining whether a second condition, that the change lasts for a predetermined time period, is satisfied, and (iii) adding up a plurality of global motion vectors with respect to a plurality of images, and determining whether a third condition, that a sum of the global motion vectors exceeds a second reference value, is satisfied; and determining occurrence of camera tempering if at least one of the corresponding conditions is satisfied.

Abstract: A method and system for detecting a motion of a target object in a thermal image by removing a shadow by heat of the target object from the thermal image. The motion detecting system includes: a learning unit obtaining at least one of size and brightness of a shadow by heat of a reference object based on characteristics of the shadow by heat of the reference object by temperature; and a detecting unit removing a shadow region of the target object from the thermal image including the target object based on at least one of the size and the brightness of the shadow by heat of the object.

Abstract: A method and a system for analyzing multi-channel images are provided. The method includes: receiving a plurality of images through a plurality of channels, respectively; combining selected images among the plurality of images into a single image; and performing an image analysis with respect to: entirety of the combined image by treating the selected images as a single image; or each of the selected images in the combined image.

Abstract: A method and system for detecting a motion of a target object in a thermal image by removing a shadow by heat of the target object from the thermal image. The motion detecting system includes: a learning unit obtaining at least one of size and brightness of a shadow by heat of a reference object based on characteristics of the shadow by heat of the reference object by temperature; and a detecting unit removing a shadow region of the target object from the thermal image including the target object based on at least one of the size and the brightness of the shadow by heat of the object.

Abstract: A method and a system for analyzing multi-channel images are provided. The method includes: receiving a plurality of images through a plurality of channels, respectively; combining selected images among the plurality of images into a single image; and performing an image analysis with respect to: entirety of the combined image by treating the selected images as a single image; or each of the selected images in the combined image.

Abstract: Disclosed herein is a system for diagnosing a deficient pulse and an forceful pulse. The system includes a pulse diagnotic device, a deficient pulse and forceful pulse determining device, and an output device. The pulse diagnotic device measures pulse condition information at an examinee's Cun (˜\f˜) Gu (H), and Chi (,R) pulse-taking locations on his or her wrist using one or more pulse-taking sensors. The deficient pulse and forceful pulse determining device is operably connected to the pulse diagnotic device, analyzes the pulse pressure information measured by the pulse diagnotic device, calculates a quantified deficiency/forceful coefficient, and determines whether a pulse of interest is a deficient pulse or an forceful pulse. The output device is connected to the determining device and displays results of the determination.

Abstract: A method and apparatus for stabilizing a locus of an object detected from a continuously-captured image, and an image monitoring system are provided. The apparatus includes: a detection unit which detects first information about the locus provided at a first time, from the continuously-captured image; a storage unit which stores second information about the locus provided at at least one other time; a correction unit which corrects the first information based on the second information; and a display unit which applies the corrected first information to the object in the continuously-captured image to display a modified locus corresponding to the corrected first information.