Patents by Inventor Eun-Ji Choi
Eun-Ji Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11551733Abstract: The present technology includes a data strobe clock output circuit. The data strobe clock output circuit includes a first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal and output a first data strobe clock in response to the rising clock, the falling clock, and mode signals, and a second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signals.Type: GrantFiled: November 4, 2020Date of Patent: January 10, 2023Assignee: SK hynix Inc.Inventors: Eun Ji Choi, Ja Yoon Goo, Sung Hwa Ok
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Publication number: 20220223188Abstract: A semiconductor apparatus includes a memory controller and data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output apparatus configure to output read data from the memory cell array by sensing a logic level of the read data during a low-level period of a first clock, which is an inverted signal of a divided clock of the clock signal, and a low-level period of a second clock, the second clock having a set to phase delay amount from the divided clock.Type: ApplicationFiled: June 7, 2021Publication date: July 14, 2022Applicant: SK hynix Inc.Inventor: Eun Ji CHOI
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Publication number: 20220103176Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Applicant: SK hynix Inc.Inventors: Jin Ha HWANG, Yo Han JEONG, Eun Ji CHOI
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Patent number: 11264064Abstract: A data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block a remaining signal path among a plurality of signal paths for transmitting data except for a signal path corresponding to a currently selected driving strength. The pre-driver may be configured to drive data, which are transmitted through the signal path corresponding to the currently selected driving strength, using an impedance determined in accordance with a plurality of impedance control codes.Type: GrantFiled: June 16, 2020Date of Patent: March 1, 2022Assignee: SK hynix Inc.Inventor: Eun Ji Choi
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Patent number: 11233512Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.Type: GrantFiled: September 10, 2020Date of Patent: January 25, 2022Assignee: SK hynix Inc.Inventors: Jin Ha Hwang, Yo Han Jeong, Eun Ji Choi
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Publication number: 20220005513Abstract: The present technology includes a data strobe dock output circuit. The data strobe clock output circuit includes a first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal and output a first data strobe clock in response to the rising clock, the falling clock, and mode signals, and a second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signals.Type: ApplicationFiled: November 4, 2020Publication date: January 6, 2022Applicant: SK hynix Inc.Inventors: Eun Ji CHOI, Ja Yoon GOO, Sung Hwa OK
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Patent number: 11190185Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.Type: GrantFiled: June 12, 2020Date of Patent: November 30, 2021Assignee: SK hynix Inc.Inventors: Eun Ji Choi, Jin Ha Hwang, Keun Seon Ahn, Yo Han Jeong
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Publication number: 20210367600Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.Type: ApplicationFiled: September 10, 2020Publication date: November 25, 2021Applicant: SK hynix Inc.Inventors: Jin Ha HWANG, Yo Han JEONG, Eun Ji CHOI
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Patent number: 11158356Abstract: Provided is a calibration circuit and operating method of the calibration circuit. A calibration circuit includes a first resistor code output circuit and a second resistor code output circuit. The first resistor code output circuit is coupled to an external resistor through an input/output pad, performs a first calibration operation, based on a first resistor value, such that a target voltage applied to a first reference node coupled to the input/output pad has a set voltage level, and outputs a first resistor code as a result obtained by performing the first calibration operation. The second resistor code output circuit receives the target voltage, sets an internal resistor value, based on the first resistor code, performs a second calibration operation, based on a second resistor value different from the first resistor value, and outputs a second resistor code as a result obtained by performing the second calibration operation. The first resistor value is a resistor value of the first resistor.Type: GrantFiled: November 13, 2020Date of Patent: October 26, 2021Assignee: SK hynix Inc.Inventors: Jin Ha Hwang, Kwan Su Shon, Keun Seon Ahn, Yo Han Jeong, Eun Ji Choi
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Publication number: 20210201962Abstract: A data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block a remaining signal path among a plurality of signal paths for transmitting data except for a signal path corresponding to a currently selected driving strength. The pre-driver may be configured to drive data, which are transmitted through the signal path corresponding to the currently selected driving strength, using an impedance determined in accordance with a plurality of impedance control codes.Type: ApplicationFiled: June 16, 2020Publication date: July 1, 2021Applicant: SK hynix Inc.Inventor: Eun Ji CHOI
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Publication number: 20210194485Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.Type: ApplicationFiled: June 12, 2020Publication date: June 24, 2021Inventors: Eun Ji CHOI, Jin Ha HWANG, Keun Seon AHN, Yo Han JEONG
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Patent number: 10847194Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.Type: GrantFiled: November 19, 2018Date of Patent: November 24, 2020Assignee: SK hynix Inc.Inventors: Dong Hyun Kim, Dae Han Kwon, Kwan Su Shon, Soon Ku Kang, Jung Hyun Shin, Doo Bock Lee, Yo Han Jeong, Eun Ji Choi, Tae Jin Hwang
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Patent number: 10742181Abstract: A buffer circuit includes a first buffer configured to operate at an external power voltage, generate first and second buffer signals by comparing an input signal with a reference voltage, and control potential levels of the first and second buffer signals in response to a common mode feedback voltage; a second buffer configured to operate at an internal power voltage and generate an output signal in response to the first and second buffer signals; and a replica circuit configured to generate the common mode feedback voltage to be less than the internal power voltage.Type: GrantFiled: October 18, 2018Date of Patent: August 11, 2020Assignee: SK hynix Inc.Inventors: Dong Hyun Kim, Eun Ji Choi, Yo Han Jeong, Jae Heung Kim
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Publication number: 20190296742Abstract: A buffer circuit includes a first buffer configured to operate at an external power voltage, generate first and second buffer signals by comparing an input signal with a reference voltage, and control potential levels of the first and second buffer signals in response to a common mode feedback voltage; a second buffer configured to operate at an internal power voltage and generate an output signal in response to the first and second buffer signals; and a replica circuit configured to generate the common mode feedback voltage to be less than the internal power voltage.Type: ApplicationFiled: October 18, 2018Publication date: September 26, 2019Inventors: Dong Hyun KIM, Eun Ji CHOI, Yo Han JEONG, Jae Heung KIM
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Publication number: 20190287587Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.Type: ApplicationFiled: November 19, 2018Publication date: September 19, 2019Inventors: Dong Hyun KIM, Dae Han KWON, Kwan Su SHON, Soon Ku KANG, Jung Hyun SHIN, Doo Bock LEE, Yo Han JEONG, Eun Ji CHOI, Tae Jin HWANG
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Patent number: 10284156Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.Type: GrantFiled: August 3, 2017Date of Patent: May 7, 2019Assignee: SK hynix Inc.Inventors: Dong Hyun Kim, Eun Ji Choi, Yo Han Jeong, Soon Ku Kang, Woo Jin Kang, Kwan Su Shon, Hyun Bae Lee, Tae Jin Hwang
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Publication number: 20180294784Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.Type: ApplicationFiled: August 3, 2017Publication date: October 11, 2018Applicant: SK hynix Inc.Inventors: Dong Hyun KIM, Eun Ji CHOI, Yo Han JEONG, Soon Ku KANG, Woo Jin KANG, Kwan Su SHON, Hyun Bae LEE, Tae Jin HWANG
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Patent number: 9997250Abstract: A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.Type: GrantFiled: October 7, 2016Date of Patent: June 12, 2018Assignee: SK Hynix Inc.Inventors: Kang-Woo Park, Eun-Ji Choi
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Patent number: 9859910Abstract: An analog to digital converter includes a first DAC unit configured to vary a level of a reference voltage output through a first node according to a first code, a second DAC unit coupled in parallel to the first DAC unit on the basis of the first node and configured to vary the level of the reference voltage according to a second code, a comparator configured to generate a comparison result signal by comparing an input voltage and the reference voltage, and at least one register array configured to store the first code and the second code with initial values and store the first code and the second code by varying values of the first code and the second code according to the comparison result signal.Type: GrantFiled: June 26, 2017Date of Patent: January 2, 2018Assignee: SK hynix Inc.Inventors: Dong Hyun Kim, Soon Ku Kang, Kwan Su Shon, Yo Han Jeong, Eun Ji Choi
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Patent number: 9830959Abstract: A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The data latch circuit may output latched data to an input/output line in response to a cell select signal. The data first stage amplification circuit may generate driving data to a voltage level of an external power supply voltage in response to a voltage level of the input/output line. The data first stage amplification circuit may precharge the input/output line to a voltage level lower than the external power supply voltage and higher than a ground voltage in response to a precharge signal.Type: GrantFiled: November 7, 2016Date of Patent: November 28, 2017Assignee: SK hynix Inc.Inventors: Kang Woo Park, Eun Ji Choi