Abstract: An oral pouch packaging material, an oral pouch manufactured using the oral pouch packaging material, and a method of preparing an oral pouch packaging material are provided. The oral pouch packaging material includes 0% by weight (wt %) to 40 wt % of a cellulose-based staple fiber, 20 wt % to 80 wt % of a pulp fiber, 20 wt % to 60 wt % of a thermoplastic resin fiber, and 0 wt % to 5 wt % of a binder, and is prepared by a wet method.

Abstract: Provided is a nicotine pouch including a filler, and a packaging material that wraps the filler, in which the filler includes nicotine, a release control excipient including at least one or more selected from a group consisting of cellulose and sugar alcohol, a binder, a pH adjuster, and a flavoring agent, a content of the nicotine in the filler is 2.5 to 10 wt % with respect to a weight of total solid contents of the filler, a content of the release control excipient in the filler is 5.5 to 36 times the content of nicotine, and the packaging material includes at least two or more selected from a group consisting of pulp, a cellulosic staple fiber, and a thermoplastic fiber.

Abstract: Provided is a nicotine pouch filler including nicotine, a release control excipient, a binder, a pH adjuster, and a flavoring agent, in which a content of the binder is 6 to 10 wt % with respect to a weight of total solid contents of the nicotine pouch filler.

Abstract: Provided is a nicotine pouch filler including nicotine, a release control excipient including at least one or more selected from a group consisting of cellulose and sugar alcohol, a binder, a pH adjuster, and a flavoring agent, wherein a content of the nicotine is 2.5 to 10 wt % with respect to a weight of total solid contents of the nicotine pouch filler, and a content of the release control excipient is 5.5 to 36 times the content of the nicotine.

Abstract: A method of packaging a nicotine pouch by forming a longitudinal seal and a cross seal of a packaging material is provided. The packaging material may include pulp and a thermoplastic resin fiber, the longitudinal seal and the cross seal may have a width of 2 millimeters (mm) to 5 mm, and a scaling temperature at which the longitudinal seal and the cross seal are formed may range from 110° C. to 160° C.

Abstract: Provided is a nicotine pouch filler including nicotine, a release control excipient, a binder, a pH adjuster, a solvent, and a flavoring agent, wherein the solvent includes one or more of water and ethanol, and the water and the ethanol are mixed at a weight ratio of 4:6 to 0:10.

Abstract: Provided is a nicotine pouch filler including nicotine, a release control excipient including at least one or more selected from a group consisting of cellulose and sugar alcohol, a binder, a pH adjuster, and a flavoring agent, in which the release control excipient includes cellulose and sugar alcohol, the cellulose and the sugar alcohol are mixed at a weight ratio of 1:9 to 5:5, the cellulose includes one or more of microcrystalline cellulose (MCC) and methyl cellulose, and the sugar alcohol includes at least one or more selected from a group consisting of erythritol, xylitol, mannitol, sorbitol, maltitol, and isomaltol.

Abstract: Provided are a filler for an oral pouch with excellent elution characteristics of an active material, and an oral pouch including the filler.

Abstract: Provided are a filler for an oral pouch including specific types and specific content of sugar alcohol, and an oral pouch including the filler.

Abstract: Provided is a packaging material for a nicotine pouch, the packaging material including a cellulose fiber, and a thermoplastic material fiber, wherein a content of the cellulose fiber is 40 to 80 wt % with respect to a total weight of the packaging material for the nicotine pouch, and a content of the thermoplastic material fiber is 20 to 60 wt % with respect to the total weight of the packaging material for the nicotine pouch.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate having a device isolation region, a first drain spacer on one side of the gate electrode, a second drain spacer next to the first drain spacer, a first source spacer on an opposite side of the gate electrode and a portion of the semiconductor substrate where a source region is to be formed, a second source spacer on side and top surfaces of the first source spacer, and LDDs adjacent to the first drain spacer and below the first source spacers, wherein the LDD below the first source spacer is thinner than the LDD adjacent to the first drain spacer.

Abstract: A method for manufacturing a semiconductor device includes can prevent defects of a semiconductor device due to the deterioration of electro migration (EM)/stress migration (SM) properties of the device as a result of metal corrosion and void generation in burying a novolac material. Embodiments can also prevent the generation of fencing in a metal wire structure.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMOS areas, a primary gate spacer formed at sides of the gate, LDD areas formed in the semiconductor substrate at sides of the gate, a secondary gate spacer formed at sides of the primary gate spacer, source and drain areas formed in the semiconductor substrate at sides of the gate of the PMOS area; and source and drain areas formed in the semiconductor substrate at sides of the gate of the NMOS area, wherein the source and drain areas of the NMOS area are deeper than the source and drain areas of the PMOS area.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a gate structure which includes a silicon oxynitride (SiON) layer formed on a semiconductor substrate, a hafnium silicon oxynitride (HfSiON) layer formed on the silicon oxynitride (SiON) layer, a polysilicon layer formed on the hafnium silicon oxynitride (HfSiON) layer, and a silicide layer formed on the polysilicon layer, spacers at sidewalls of the gate structure, and source and drain regions at opposite sides of the gate structure.

Abstract: The present disclosure relates to a semiconductor device and a method of forming the semiconductor device that includes forming a gate insulating film on a semiconductor substrate, forming a polysilicon layer containing fluorine on the gate insulating film, forming a gate pattern by patterning the gate insulating film and the polysilicon layer, forming a metal layer on the semiconductor substrate including the gate pattern, and reacting the metal layer with the patterned polysilicon layer to form an FUSI dual gate having a lower Si-rich silicide layer and an upper Ni-rich silicide layer. The present method can reliably control a work function of an FUSI dual gate formed thereby, improve a device performance and an NBTI characteristic by preventing Vfb from shifting. The present invention is generally applicable to high performance devices, as well as lower power devices and memory devices.

Abstract: A method for manufacturing a semiconductor device, including etching exposed areas of a substrate using patterned nitride and insulating layers as an etch mask to form a trench in the substrate; forming a buffer layer in the trench; forming a stress-inducing layer by implanting ions into a region of the substrate around the trench using the patterned nitride and insulating layers as an ion implant mask; forming a device isolation region by filling the trench with an trench insulating layer; and removing the patterned nitride and insulating layers.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device can include a transistor structure, including a gate dielectric on a substrate, a gate electrode on the gate dielectric, a spacer at sidewalls of the gate electrode, and source/drain regions in the substrate; and an interlayer dielectric on the transistor structure where an air gap is provided in a region between the spacer, the interlayer dielectric, and the source/drain region of the substrate.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMOS areas, a primary gate spacer formed at sides of the gate, LDD areas formed in the semiconductor substrate at sides of the gate, a secondary gate spacer formed at sides of the primary gate spacer, source and drain areas formed in the semiconductor substrate at sides of the gate of the PMOS area; and source and drain areas formed in the semiconductor substrate at sides of the gate of the NMOS area, wherein the source and drain areas of the NMOS area are deeper than the source and drain areas of the PMOS area.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having first and second active areas defined thereon by isolation layers, a first gate electrode in the first active area, in which the first gate electrode includes a first silicide, and a second gate electrode in the second active area, in which the second gate electrode includes a second silicide having a composition ratio of silicon different from a composition ratio of silicon of the first silicide.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate having a device isolation region, a first drain spacer on one side of the gate electrode, a second drain spacer next to the first drain spacer, a first source spacer on an opposite side of the gate electrode and a portion of the semiconductor substrate where a source region is to be formed, a second source spacer on side and top surfaces of the first source spacer, and LDDs adjacent to the first drain spacer and below the first source spacers, wherein the LDD below the first source spacer is thinner than the LDD adjacent to the first drain spacer.