Abstract: A multiblock copolymer, a method for preparing same, and a thermoplastic resin composition comprising polypropylene and the multiblock copolymer are described herein. The block copolymer has excellent processability and excellent compatibility with polypropylene, and the thermoplastic resin composition of the present disclosure using the same shows excellent low temperature impact strength and may be usefully used as a thermoplastic resin composition for the manufacture of a product requiring high impact resistance such as automotive parts.

Abstract: Provided is a method for preparing a pouch filling material including step S1 of preparing a solid-phase filling material including a binder, step S2 of preparing a particle size control solution including a processing aid, and step S3 of spraying the particle size control solution onto the solid-phase filling material while stirring the solid-phase filling material.

Abstract: A method for manufacturing a semiconductor device includes can prevent defects of a semiconductor device due to the deterioration of electro migration (EM)/stress migration (SM) properties of the device as a result of metal corrosion and void generation in burying a novolac material. Embodiments can also prevent the generation of fencing in a metal wire structure.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate having a device isolation region, a first drain spacer on one side of the gate electrode, a second drain spacer next to the first drain spacer, a first source spacer on an opposite side of the gate electrode and a portion of the semiconductor substrate where a source region is to be formed, a second source spacer on side and top surfaces of the first source spacer, and LDDs adjacent to the first drain spacer and below the first source spacers, wherein the LDD below the first source spacer is thinner than the LDD adjacent to the first drain spacer.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMOS areas, a primary gate spacer formed at sides of the gate, LDD areas formed in the semiconductor substrate at sides of the gate, a secondary gate spacer formed at sides of the primary gate spacer, source and drain areas formed in the semiconductor substrate at sides of the gate of the PMOS area; and source and drain areas formed in the semiconductor substrate at sides of the gate of the NMOS area, wherein the source and drain areas of the NMOS area are deeper than the source and drain areas of the PMOS area.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a gate structure which includes a silicon oxynitride (SiON) layer formed on a semiconductor substrate, a hafnium silicon oxynitride (HfSiON) layer formed on the silicon oxynitride (SiON) layer, a polysilicon layer formed on the hafnium silicon oxynitride (HfSiON) layer, and a silicide layer formed on the polysilicon layer, spacers at sidewalls of the gate structure, and source and drain regions at opposite sides of the gate structure.

Abstract: The present disclosure relates to a semiconductor device and a method of forming the semiconductor device that includes forming a gate insulating film on a semiconductor substrate, forming a polysilicon layer containing fluorine on the gate insulating film, forming a gate pattern by patterning the gate insulating film and the polysilicon layer, forming a metal layer on the semiconductor substrate including the gate pattern, and reacting the metal layer with the patterned polysilicon layer to form an FUSI dual gate having a lower Si-rich silicide layer and an upper Ni-rich silicide layer. The present method can reliably control a work function of an FUSI dual gate formed thereby, improve a device performance and an NBTI characteristic by preventing Vfb from shifting. The present invention is generally applicable to high performance devices, as well as lower power devices and memory devices.

Abstract: A method for manufacturing a semiconductor device, including etching exposed areas of a substrate using patterned nitride and insulating layers as an etch mask to form a trench in the substrate; forming a buffer layer in the trench; forming a stress-inducing layer by implanting ions into a region of the substrate around the trench using the patterned nitride and insulating layers as an ion implant mask; forming a device isolation region by filling the trench with an trench insulating layer; and removing the patterned nitride and insulating layers.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device can include a transistor structure, including a gate dielectric on a substrate, a gate electrode on the gate dielectric, a spacer at sidewalls of the gate electrode, and source/drain regions in the substrate; and an interlayer dielectric on the transistor structure where an air gap is provided in a region between the spacer, the interlayer dielectric, and the source/drain region of the substrate.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMOS areas, a primary gate spacer formed at sides of the gate, LDD areas formed in the semiconductor substrate at sides of the gate, a secondary gate spacer formed at sides of the primary gate spacer, source and drain areas formed in the semiconductor substrate at sides of the gate of the PMOS area; and source and drain areas formed in the semiconductor substrate at sides of the gate of the NMOS area, wherein the source and drain areas of the NMOS area are deeper than the source and drain areas of the PMOS area.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate having a device isolation region, a first drain spacer on one side of the gate electrode, a second drain spacer next to the first drain spacer, a first source spacer on an opposite side of the gate electrode and a portion of the semiconductor substrate where a source region is to be formed, a second source spacer on side and top surfaces of the first source spacer, and LDDs adjacent to the first drain spacer and below the first source spacers, wherein the LDD below the first source spacer is thinner than the LDD adjacent to the first drain spacer.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having first and second active areas defined thereon by isolation layers, a first gate electrode in the first active area, in which the first gate electrode includes a first silicide, and a second gate electrode in the second active area, in which the second gate electrode includes a second silicide having a composition ratio of silicon different from a composition ratio of silicon of the first silicide.

Abstract: A method for forming contacts of a semiconductor device is provided. A diffusion barrier layer, an interlayer insulating layer, and a capping layer are sequentially formed on a lower metal wiring layer. A hard mask layer is formed on the capping layer. A photoresist layer is formed and patterned to form vias. Vias are formed by sequentially etching the hard mask, capping, and interlayer insulating layers using the patterned photoresist layer as an etch mask until the diffusion barrier layer is exposed. A metal layer is deposited in the vias to form contacts. The metal and hard mask layers are removed until the capping layer is exposed. This prevents tapering at top of the capping layer during plasma treatment, thus preventing tungsten bridges that may occur through margins of vias when a CMOS device with a strict design rule is manufactured and improving electrical characteristics and reliability of semiconductor devices.

Abstract: A nonvolatile memory device and a method for fabricating the same decreases power consumption and prevents contamination of an insulating layer. The nonvolatile memory device includes a semiconductor substrate; a tunneling oxide layer formed on a predetermined portion of the semiconductor substrate; a floating gate formed on the tunneling oxide layer, the floating gate having a trench structure; a control gate formed inside the trench structure of the floating gate; and a gate insulating layer disposed between the floating gate and the control gate.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a gate structure which includes a silicon oxynitride (SiON) layer formed on a semiconductor substrate, a hafnium silicon oxynitride (HfSiON) layer formed on the silicon oxynitride (SiON) layer, a polysilicon layer formed on the hafnium silicon oxynitride (HfSiON) layer, and a silicide layer formed on the polysilicon layer, spacers at sidewalls of the gate structure, and source and drain regions at opposite sides of the gate structure.

Abstract: A method for manufacturing a semiconductor device includes can prevent defects of a semiconductor device due to the deterioration of electro migration (EM)/stress migration (SM) properties of the device as a result of metal corrosion and void generation in burying a novolac material. Embodiments can also prevent the generation of fencing in a metal wire structure.

Abstract: A method for manufacturing a semiconductor device, including etching exposed areas of a substrate using patterned nitride and insulating layers as an etch mask to form a trench in the substrate; forming a buffer layer in the trench; forming a stress-inducing layer by implanting ions into a region of the substrate around the trench using the patterned nitride and insulating layers as an ion implant mask; forming a device isolation region by filling the trench with an trench insulating layer; and removing the patterned nitride and insulating layers.

Abstract: A method for fabricating a flash memory device is disclosed that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern, which includes forming a sacrificial insulating pattern layer over a flash memory channel region of a semiconductor substrate; forming source and drain regions in the semiconductor substrate by ion implantation using the sacrificial insulating pattern layer as a mask; removing portions of the sacrificial insulating pattern layer; sequentially forming an ONO-type dielectric layer and a gate material layer; selectively etching the gate material layer and at least part of the gate dielectric layer to form a gate; and forming gate sidewall spacers at sides of the gate.

Abstract: A method of forming a shallow trench isolation includes sequentially forming a pad oxide layer and a pad nitride layer over a semiconductor substrate. A portion of the pad nitride layer is etched and patterned. The patterned pad nitride layer is used as a etching mask to etch the pad oxide layer and the semiconductor substrate, thus forming a trench. An oxide layer is formed over the surface of the trench by an oxidation process. A barrier liner layer is formed over the oxide layer to create a tensile stress in a vertical direction to the semiconductor substrate. The trench is filled with insulation material and then planarized to expose a top face of the patterned pad nitride layer. A shallow trench isolation structure is completed by removing the patterned pad nitride layer and pad oxide layer. The process prevents a divot effect cased on an edge area of shallow trench isolation structure.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device can include a transistor structure, including a gate dielectric on a substrate, a gate electrode on the gate dielectric, a spacer at sidewalls of the gate electrode, and source/drain regions in the substrate; and an interlayer dielectric on the transistor structure where an air gap is provided in a region between the spacer, the interlayer dielectric, and the source/drain region of the substrate.