Patents by Inventor Eun Ju CHOE

Eun Ju CHOE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interface device supporting test operation
    Patent number: 12250009
    Abstract: Disclosed is an interface circuit including a first parallel-to-serial conversion circuit suitable for converting inverted parallel data in a parallel-to-serial manner to generate first output data in a test mode; a second parallel-to-serial conversion circuit suitable for converting non-inverted parallel data in the parallel-to-serial manner to generate second output data in the test mode; a third parallel-to-serial conversion circuit suitable for converting the non-inverted parallel data in the parallel-to-serial manner to generate third output data in the test mode; a fourth parallel-to-serial conversion circuit suitable for converting the inverted parallel data in the parallel-to-serial manner to generate fourth output data in the test mode; a first driver circuit suitable for receiving the first and second output data in the test mode; and a second driver circuit suitable for receiving the third and fourth output data in the test mode.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 11, 2025
    Assignee: SK hynix Inc.
    Inventors: Eun Ju Choe, Ho Young Park, Jong Hwan Choi
  • INTERFACE DEVICE SUPPORTING TEST OPERATION
    Publication number: 20240146329
    Abstract: Disclosed is an interface circuit including a first parallel-to-serial conversion circuit suitable for converting inverted parallel data in a parallel-to-serial manner to generate first output data in a test mode; a second parallel-to-serial conversion circuit suitable for converting non-inverted parallel data in the parallel-to-serial manner to generate second output data in the test mode; a third parallel-to-serial conversion circuit suitable for converting the non-inverted parallel data in the parallel-to-serial manner to generate third output data in the test mode; a fourth parallel-to-serial conversion circuit suitable for converting the inverted parallel data in the parallel-to-serial manner to generate fourth output data in the test mode; a first driver circuit suitable for receiving the first and second output data in the test mode; and a second driver circuit suitable for receiving the third and fourth output data in the test mode.
    Type: Application
    Filed: March 15, 2023
    Publication date: May 2, 2024
    Inventors: Eun Ju CHOE, Ho Young PARK, Jong Hwan CHOI