Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.

Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.

Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.

Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.

Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.

Abstract: A method for preparing amino linker oligonucleotides is provided. More specifically, a method of preparing 5?-amino-linker oligonucleotides comprising the steps of: introducing an amino linker having a protecting group into the 5? terminus of an oligonucleotide; and removing the protecting group from the amino linker oligonucleotide by contacting with acetic acid and 2,2,2-trifluoroethanol is provided. The amino protecting group is efficiently removed from the amino linker oligonucleotides, and thereby achieving a high yield of the amino linker oligonucleotides.

Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.

Abstract: A method for preparing amino linker oligonucleotides is provided, wherein an amino protecting group is efficiently removed from the amino linker oligonucleotides protected by the protecting group, and thereby achieving a high yield of the amino linker oligonucleotides.

Abstract: A delay locked loop(DLL) includes a phase detector for detecting phase difference between input clock signals and feedback clock signals, and outputting phase detection signals according to results of the detection, a delay line for delaying the input clock signals in response to first and second delay control signals, and outputting delay clock signals, a delay controller for generating the first and the second delay control signals in response to the phase detection signals, and a delay model for delaying reference clock signals during predetermined time, and outputting the delayed signals as the feedback clock signals.

Abstract: The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.

Abstract: A DLL with a reduced size, a semiconductor memory device including the DLL and a locking operation method of the DLL that includes a phase detector, a delay line, a delay controller, a delay circuit and an output buffer. The phase detector detects phase difference between input clock signals and feedback clock signals, and outputs phase detection signals according to results of the detection. The delay circuit delays reference clock signals during predetermined time and outputs the delayed signals as feedback clock signals. The output buffer outputs internal clock signals in response to delay clock signals. The reference clock signals are generated by one of circuits that exist in an actual output path of the internal clock signals. Accordingly, it is possible to reduce skew between the data strobe signals/the output data signals and the external clock signals, which may occur according to conditions in manufacturing processes, and to reduce the occupation area of the DLL.

Abstract: The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.

Abstract: A semiconductor memory device includes a clock enable signal self refresh buffer for generating a self refresh clock enable signal by receiving the clock enable signal in the self refresh mode, an internal clock signal generating unit for generating an internal clock signal by receiving the external clock signal, a signal synchronization unit for generating an internal clock enable signal by synchronizing the clock enable signal with the internal clock signal, a level detection unit for generating a level detection signal by detecting levels of the internal clock enable signal and the self refresh clock enable signal, a clock self refresh buffer for receiving the external clock signal during a self refresh mode in response to the level detection signal, and a self refresh command generation unit for activating a self refresh command in response to the level detection signal and inactivating the self refresh command in response to the level detection signal and an output signal of the clock self refresh buffer

Abstract: A memory device minimizes the skew between an external clock and a DQS (or DQ) after the locking state by regulating a delay ratio of a replica delay model to compensate errors of process, temperature or voltage change. The memory device comprises: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer. Here, the DLL comprises a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to a plurality of control signals inputted externally in a test mode.

Abstract: A semiconductor memory device includes a clock enable signal self refresh buffer for generating a self refresh clock enable signal by receiving the clock enable signal in the self refresh mode, an internal clock signal generating unit for generating an internal clock signal by receiving the external clock signal, a signal synchronization unit for generating an internal clock enable signal by synchronizing the clock enable signal with the internal clock signal, a level detection unit for generating a level detection signal by detecting levels of the internal clock enable signal and the self refresh clock enable signal, a clock self refresh buffer for receiving the external clock signal during a self refresh mode in response to the level detection signal, and a self refresh command generation unit for activating a self refresh command in response to the level detection signal and inactivating the self refresh command in response to the level detection signal and an output signal of the clock self refresh buffer