Patents by Inventor Eun-Kuk Chung
Eun-Kuk Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8419853Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.Type: GrantFiled: November 23, 2009Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
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Patent number: 7682450Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.Type: GrantFiled: July 13, 2006Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
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Publication number: 20100065912Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.Type: ApplicationFiled: November 23, 2009Publication date: March 18, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun-Seung KANG, Eun-Kuk CHUNG, Joon KIM, Jin-Hong KIM, Suk-Chul BANG
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Patent number: 7585757Abstract: In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.Type: GrantFiled: June 5, 2006Date of Patent: September 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Seon Ahn, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Eun-Kuk Chung, Hyung-Mo Yang, Chang-Yeon Yoo, Yun-Seung Kang, Kyung-Tae Jang
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Publication number: 20080176374Abstract: A method of fabricating a semiconductor device using a self-aligned metal shunt process is disclosed. The method can include sequentially forming a lower conductive pattern and a sacrificial pattern on a semiconductor substrate. An interlayer dielectric layer is formed to cover the sacrificial pattern. The interlayer dielectric layer is patterned to form a preliminary trench that exposes the top surface of the sacrificial pattern. The exposed sacrificial pattern is removed to form a trench that expose the top surface of the lower conductive pattern. An upper conductive pattern is formed to fill the trench.Type: ApplicationFiled: January 23, 2008Publication date: July 24, 2008Inventors: Yeol Jon, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim
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Publication number: 20080087933Abstract: Example embodiments relate to a semiconductor memory device including a channel layer pattern on a substrate, the channel layer pattern having a sidewall and an upper face, a spacer on the sidewall of the channel layer pattern, and a gate electrode covering the sidewall of the channel layer pattern, the spacer and the upper face of the channel layer pattern.Type: ApplicationFiled: September 27, 2007Publication date: April 17, 2008Inventors: Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Jong-Seon Ahn
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Publication number: 20070281434Abstract: According to embodiments of the invention, a height of a capacitor lower electrode is increased. Portions of the lower electrode and an interlayer insulating layer are etched within the interlayer insulating layer that is formed with the lower electrode thereon, so that a trench having a double damascene structure is formed. A dielectric layer and an upper electrode are formed within the trench. Therefore, shorts between metal interconnects caused by misalignments during formation of the upper electrode are prevented and consistent capacitance values may be secured.Type: ApplicationFiled: August 20, 2007Publication date: December 6, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Seon AHN, Joon KIM, Suk-Chul BANG, Sang-Hoon LEE, Yung-Jun KIM, Woo-Soon JANG, Eun-Kuk CHUNG
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Patent number: 7268029Abstract: Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.Type: GrantFiled: November 19, 2004Date of Patent: September 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-kuk Chung, Joon Kim, Suk-Chul Bang, Jong-Sun Ahn, Sang-hoon Lee, Woo-soon Jang, Yung-jun Kim
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Publication number: 20070023794Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.Type: ApplicationFiled: July 13, 2006Publication date: February 1, 2007Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
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Publication number: 20060281290Abstract: In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.Type: ApplicationFiled: June 5, 2006Publication date: December 14, 2006Inventors: Jong-Seon Ahn, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Eun-Kuk Chung, Hyung-Mo Yang, Chang-Yeon Yoo, Yun-Seung Kang, Kyung-Tae Jang
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Patent number: 7049197Abstract: In a method of manufacturing a semiconductor device including independent gate patterns separated from each other, an active region is defined by forming a field region on a substrate. A gate oxide layer and a polysilicon layer are formed on the substrate. A preliminary gate pattern is formed by partially removing the polysilicon layer along a first direction by a first etching process. A spacer is formed along a side surface of the preliminary gate pattern. A number of separated gate patterns is formed by partially removing the preliminary gate pattern along a second direction crossing the first direction by a second etching process. The gate patterns overlap with the active regions and are separated from each other. Therefore, the overlap margin is increased, and the polysilicon layer is prevented from being over-etched when it is patterned to form the gate pattern.Type: GrantFiled: October 28, 2004Date of Patent: May 23, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Soon Jang, Joon Kim, Eun-Kuk Chung
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Patent number: 7008876Abstract: A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.Type: GrantFiled: December 30, 2003Date of Patent: March 7, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Sung Lee, Bong-Hyun Kim, Myang-Sik Han, Eun-Kuk Chung
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Publication number: 20050164455Abstract: In a method of manufacturing a semiconductor device including independent gate patterns separated from each other, an active region is defined by forming a field region on a substrate. A gate oxide layer and a polysilicon layer are formed on the substrate. A preliminary gate pattern is formed by partially removing the polysilicon layer along a first direction by a first etching process. A spacer is formed along a side surface of the preliminary gate pattern. A number of separated gate patterns is formed by partially removing the preliminary gate pattern along a second direction crossing the first direction by a second etching process. The gate patterns overlap with the active regions and are separated from each other. Therefore, the overlap margin is increased, and the polysilicon layer is prevented from being over-etched when it is patterned to form the gate pattern.Type: ApplicationFiled: October 28, 2004Publication date: July 28, 2005Inventors: Woo-Soon Jang, Joon Kim, Eun-Kuk Chung
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Publication number: 20050112814Abstract: Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.Type: ApplicationFiled: November 19, 2004Publication date: May 26, 2005Inventors: Eun-kuk Chung, Joon Kim, Suk-Chul Bang, Jong-Sun Ahn, Sang-hoon Lee, Woo-soon Jang, Yung-jun Kim
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Publication number: 20050110143Abstract: According to embodiments of the invention, a height of a capacitor lower electrode is increased. Portions of the lower electrode and an interlayer insulating layer are etched within the interlayer insulating layer that is formed with the lower electrode thereon, so that a trench having a double damascene structure is formed. A dielectric layer and an upper electrode are formed within the trench. Therefore, shorts between metal interconnects caused by misalignments during formation of the upper electrode are prevented and consistent capacitance values may be secured.Type: ApplicationFiled: November 19, 2004Publication date: May 26, 2005Inventors: Jong-Seon Ahn, Joon Kim, Suk Bang, Sang-Hoon Lee, Yung-Jun Kim, Woo-Soon Jang, Eun-Kuk Chung
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Publication number: 20040166616Abstract: A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.Type: ApplicationFiled: December 30, 2003Publication date: August 26, 2004Inventors: Woo-Sung Lee, Bong-Hyun Kim, Myang-Sik Han, Eun-Kuk Chung