Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

Abstract: Provided is a method of solubilizing a poorly soluble/insoluble active material through formation of an oligomer composite, in which a structure having a hydrophobic cavity structure is formed by using oligomers derived from two types of hydrophilic natural polymers and a poorly soluble/insoluble component is encapsulated in the cavity structure, and thus, self-aggregation of the poorly soluble/insoluble material is prevented and simultaneously, thermodynamic stability increases to effectively solubilize the poorly soluble/insoluble material.

Abstract: A fin-shaped active region is defined on a substrate. First and second gate electrodes crossing the fin-shaped active region are arranged. A dummy gate electrode is formed between the first and second gate electrodes. A first drain region is formed between the first gate electrode and the dummy gate electrode. A second drain region is formed between the dummy gate electrode and the second gate electrode. A source region facing the second drain region is formed. A first drain plug relatively close to the dummy gate electrode, relatively far from the second gate electrode, and connected to the second drain region is formed. The second gate electrode is arranged between the second drain region and the source region. Each of the first and second gate electrodes covers a side surface of the fin-shaped active region.

Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

Abstract: Provided is a method of solubilizing a poorly soluble/insoluble active material through formation of an oligomer composite, in which a structure having a hydrophobic cavity structure is formed by using oligomers derived from two types of hydrophilic natural polymers and a poorly soluble/insoluble component is encapsulated in the cavity structure, and thus, self-aggregation of the poorly soluble/insoluble material is prevented and simultaneously, thermodynamic stability increases to effectively solubilize the poorly soluble/insoluble material.

Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.

Abstract: An electrostatic discharge element includes a first diode and a second diode. The first diode has a first well region formed in a substrate, a P-type ion-implanted region formed in the first well region, an N-type ion-implanted region formed in the first well region and spaced from the P-type ion-implanted region by a predetermined first distance, and a first intermediate layer formed on a portion of the first well region corresponding to the predetermined first distance. The second diode has a second well region form in the substrate, a P-type ion-implanted region formed in the second well region, an N-type ion-implanted region formed in the second well region and spaced from the P-type ion-implanted region by a predetermined second distance, and a second intermediate layer formed on a portion of the second well region corresponding to the predetermined second distance.

Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.

Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.

Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.