Abstract: A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circuits for controlling two spare memory cell rows, wherein word line control signals for controlling corresponding word lines connected to memory cells in a memory cell array are shifted upward and downward to control respective next word lines, thereby replacing two defective memory cell rows with the two spare memory cell rows.

Abstract: A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circuits for controlling two spare memory cell rows, wherein word line control signals for controlling corresponding word lines connected to memory cells in a memory cell array are shifted upward and downward to control respective next word lines, thereby replacing two defective memory cell rows with the two spare memory cell rows.

Abstract: A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circuits for controlling two spare memory cell rows, wherein word line control signals for controlling corresponding word lines connected to memory cells in a memory cell array are shifted upward and downward to control respective next word lines, thereby replacing two defective memory cell rows with the two spare memory cell rows.

Abstract: A sense amplifier driver circuit for generating a sense amplifier enable signal that enables a sense amplifier that drives a bit line coupled to a pass transistor of a memory cell includes an inverter that generates the sense amplifier enable signal, the inverter comprising a plurality of series-connected MOS transistors of the same conductivity type as the pass transistor. The plurality of series-connected MOS transistors may have an overall channel width/length ratio that is substantially the same as a channel width/length ratio of the pass transistor. The aggregate length of the series-connected transistors may be substantially the same as a length of the pass transistor, and widths of the series-connected transistors may be different from a width of the pass transistor.

Abstract: A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circuits for controlling two spare memory cell rows, wherein word line control signals for controlling corresponding word lines connected to memory cells in a memory cell array are shifted upward and downward to control respective next word lines, thereby replacing two defective memory cell rows with the two spare memory cell rows.

Abstract: A sense amplifier driver circuit for generating a sense amplifier enable signal that enables a sense amplifier that drives a bit line coupled to a pass transistor of a memory cell includes an inverter that generates the sense amplifier enable signal, the inverter comprising a plurality of series-connected MOS transistors of the same conductivity type as the pass transistor. The plurality of series-connected MOS transistors may have an overall channel width/length ratio that is substantially the same as a channel width/length ratio of the pass transistor. The aggregate length of the series-connected transistors may be substantially the same as a length of the pass transistor, and widths of the series-connected transistors may be different from a width of the pass transistor.