Abstract: A semiconductor device may include a substrate, a vertical channel, a gate electrode, and a conductive layer. The vertical channel may have a tube shape extending in a direction perpendicular to a surface of the substrate. The gate electrode may face the vertical channel with an outer insulating layer therebetween on an outer circumferential surface of the vertical channel. The conductive layer may face the vertical channel with an inner insulating layer therebetween on an inner circumferential surface of the vertical channel.

Abstract: Provided is a semiconductor device including a substrate, a first vertical channel, a spacer, and a second vertical channel. The first vertical channel may have a sheet shape extending in a direction perpendicular to a surface of the substrate. The spacer may be provided at an end of the first vertical channel in an extension direction. The second vertical channel may be aligned with the first vertical channel on the spacer and have a sheet shape extending in a vertical direction.

Abstract: A semiconductor device includes a dielectric wall provided in a direction perpendicular to a substrate, a first metal oxide field effect transistor (MOSFET) provided on one side surface of the dielectric wall, a second MOSFET provided above the first MOSFET in a direction perpendicular to the substrate, and a third MOSFET provided in parallel with the first MOSFET on the other side surface of the dielectric wall.

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a source electrode provided on a substrate, a drain electrode disposed away from the source electrode, and a channel connected between the source electrode and the drain electrode, wherein the channel includes a plurality of first channel layers and plurality of second channel layers, and the gate electrode is provided on one surface and another surface of each of the plurality of the first channel layers and on one surface and another surface of each of the plurality of the second channel layers.

Abstract: Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

Abstract: A semiconductor device according to an embodiment may include a substrate, an adhesive layer, and a semiconductor layer. The semiconductor layer includes a 2D material having a layered structure. The adhesive layer is interposed between the substrate and the semiconductor layer, and has adhesiveness to a 2D material.

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

Abstract: Disclosed are a semiconductor device, a method of manufacturing the same, and an electronic element and an electronic apparatus each including the semiconductor device. The semiconductor device may include a substrate, a channel layer on the substrate, a first electrode and a second electrode on two opposite ends of the channel layer, respectively, and spaced apart from each other, a gate electrode on the channel layer and spaced apart from the first electrode and the second electrode, a gate dielectric material provided between the channel layer and the gate electrode, and a chalcogen compound layer being at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer.

Abstract: Provided are a field effect transistor, a method of manufacturing the field effect transistor, and an electronic device and an electronic apparatus each including the field effect transistor. The field effect transistor includes a channel layer disposed on a substrate, a high-k gate insulating layer disposed on the channel layer, a first composite electrode layer connected to a first side of the channel layer, a second composite electrode layer connected to a second side of the channel layer, and a gate electrode layer disposed on the gate insulating layer. At least one of the first and second composite electrode layers includes a contact resistance reducing layer in contact with the channel layer and a conductive layer in contact with the contact resistance reducing layer. The conductive layer is spaced apart from the channel layer.

Abstract: A semiconductor device may include a first electrode and a second electrode on a substrate and arranged perpendicular to a surface of the substrate, a plurality of channel layers between the first electrode and the second electrode, and a gate electrode surrounding the plurality of channel layers. The plurality of channel layers may be inclined with respect to a direction from the first electrode to the second electrode. An electronic device may include the semiconductor device.

Abstract: A semiconductor device may include a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional semiconductor material, a gate dielectric layer on a first area of the channel layer, a gate electrode on the gate dielectric layer, and source and drain electrodes in a second area of the channel layer. The gate dielectric layer may include a high-k dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer may be between the high-k dielectric layer and the channel layer. A dielectric constant of the intermediate dielectric layer may be less than a dielectric constant of the high-k dielectric layer.

Abstract: A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

Abstract: A graphene manufacturing apparatus includes a reaction chamber a substrate supporter configured to structurally support a substrate inside the reaction chamber; a plasma generator configured to generate a plasma inside the reaction chamber; a first gas supply configured to supply an inert gas into the reaction chamber at a first height from an upper surface of the substrate supporter in a height direction of the reaction chamber; a second gas supply configured to supply a carbon source into the reaction chamber at a second height from the upper surface of the substrate supporter in the height direction of the reaction chamber; and a third gas supply configured to supply a reducing gas into the reaction chamber, wherein the first to third gas supply units are disposed at different heights at a third height from the upper surface of the substrate supporter in the height direction of the reaction chamber.

Abstract: A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

Abstract: A semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a gate insulating layer on a center portion of the channel layer, a gate electrode on the gate insulating layer, and a first conductive layer and a second conductive layer respectively contacting opposite sides of the channel layer. Each of the first and second conductive layers may include metal boride.

Abstract: Example embodiments relate to an image sensor configured to achieve a high photoelectric conversion efficiency and a low dark current. The image sensor includes first and second electrodes, a plurality of photodetection layers provided between the first and second electrodes, and an interlayer provided between the photodetection layers. The photodetection layers convert incident light into an electrical signal and include a semiconductor material. The interlayer includes a metallic or semi metallic material having anisotropy in electrical conductivity.

Abstract: A semiconductor device may include a substrate including a source region and a drain region in a trench, a gate insulating layer in the trench, and a gate electrode in the trench. The gate electrode may include a lower filling portion and an upper filling portion surrounded by the gate insulating layer. The lower filling portion may include a first conductive layer surrounded by the gate insulating layer and may fill a lower region of the trench. The upper filling portion may include a second conductive layer surrounded by the gate insulating layer and may fill an upper region of the trench. The first conductive layer may include graphene doped with metal.

Abstract: A semiconductor device may include a substrate including a source area and a drain area separated by a trench; a gate insulating layer in the trench; and a gate electrode. The gate electrode may include a lower buried portion and an upper buried portion in the trench. The lower buried portion may include a first conductive layer, and the upper buried portion may include a two-dimensional (2D) material layer and a second conductive layer. The second conductive layer may include a transition metal. The first conductive layer may include a transition metal identical to the transition metal included in the second conductive layer. The 2D material layer may include a chalcogen compound of a transition metal which is identical to the transition metal in the second conductive layer.

Abstract: A semiconductor device may include a first semiconductor layer including a first semiconductor material; a metal layer facing the first semiconductor layer and having conductivity; a 2D material layer between the first semiconductor layer and the metal layer; and a second semiconductor layer between the first semiconductor layer and the 2D material layer. The second semiconductor layer may include a second semiconductor material different from the first semiconductor material. The second semiconductor layer and the 2D material layer may be in direct contact with each other. The second semiconductor material may include germanium.

Abstract: The present invention relates to a 3-((8-((1H-pyrazol-4-yl)amino)imidazo[1,2-a]pyridin-3-yl)ethynyl)-N-phenylbenzamide derivative, a method for preparing the same, and a pharmaceutical composition comprising the same as an active ingredient for preventing or treating cancer. The derivative can significantly inhibit the proliferation of cancer cells by inhibiting kinases, particularly Bcr-Abl kinase or Bcr-Abl (T315I) kinase. Therefore, the derivative can be effectively used as a pharmaceutical composition for the prevention or treatment of cancer.