Patents by Inventor Eun-Mi Hong
Eun-Mi Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145173Abstract: A method of manufacturing a multilayer electronic component, the method includes, attaching a margin portion green sheet including a ceramic material, a photocuring agent, and a photoinitiator to at least one end surface of each of the plurality of cut ceramic green sheet stacked bodies in the third direction, an energy irradiation operation of irradiating, with energy, the margin portion green sheet to generate a photocuring polymerization reaction between the photocuring agent and the photoinitiator.Type: ApplicationFiled: June 2, 2023Publication date: May 2, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ji Hyeon LEE, Jong Ho LEE, Eun Jung LEE, Yong Min HONG, Yong PARK, Min Woo KIM, Jung Tae PARK, Sun Mi KIM, Sim Chung KANG
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Publication number: 20240112864Abstract: A method of manufacturing a multilayer electronic component includes cutting a stack, in which internal electrode patterns and ceramic green sheets are alternately stacked in a stacking direction, to obtain unit chips and attaching a portion of a ceramic green sheet for a side margin portion to the unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet to the unit chips by compression between a first elastic body on which the ceramic green sheet is disposed and the unit chips. The first elastic body includes a first elastic layer having and a second elastic layer having an elastic modulus different from the first elastic layer, and disposed between the unit chips and the first elastic layer. An elastic modulus of the first elastic body is greater than 50 MPa and less than or equal to 1000 MPa.Type: ApplicationFiled: July 10, 2023Publication date: April 4, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong PARK, Jung Tae PARK, Jong Ho LEE, Eun Jung LEE, Yong Min HONG, Jung Jin PARK, Rak Hyeon BAEK, Sun Mi KIM, Yong Ung LEE
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Patent number: 11944661Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.Type: GrantFiled: February 7, 2018Date of Patent: April 2, 2024Assignee: JEONNAM BIOINDUSTRY FOUNDATIONInventors: Chul Yung Choi, Dool Ri Oh, Yu Jin Kim, Eun Jin Choi, Hyun Mi Lee, Dong Hyuck Bae, Kyo Nyeo Oh, Myung-A Jung, Ji Ae Hong, Kwang Su Kim, Hu Won Kang, Jae Yong Kim, Sang O Pan, Sung Yoon Park, Rack Seon Seong
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Patent number: 9815840Abstract: The present invention relates to a pyrrolopyridazine derivative represented by Formula 1 of the detailed description, or a pharmaceutically acceptable salt thereof. The compound according to the present invention and a pharmaceutically acceptable salt thereof can inhibit the activity of protein kinase(s), and thus are useful for preventing or treating diseases related thereto.Type: GrantFiled: August 29, 2014Date of Patent: November 14, 2017Assignee: The Asan FoundationInventors: Tae Gon Baik, Won-Hyuk Jung, Seung In Kim, Seung Chan Kim, Sook Kyung Park, Su Yeon Jung, Seung Hee Ji, So Young Ki, Min Cheol Kim, Eun Young Lee, Eun Mi Hong
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Publication number: 20160207931Abstract: The present invention relates to a pyrrolopyridazine derivative represented by Formula 1 of the detailed description, or a pharmaceutically acceptable salt thereof. The compound according to the present invention and a pharmaceutically acceptable salt thereof can inhibit the activity of protein kinase(s), and thus are useful for preventing or treating diseases related thereto.Type: ApplicationFiled: August 29, 2014Publication date: July 21, 2016Applicant: CJ Healthcare CorporationInventors: Tae Gon BAIK, Won-Hyuk JUNG, Seung In KIM, Seung Chan KIM, Sook Kyung PARK, Su Yeon JUNG, Seung Hee JI, So Young KI, Min Cheol KIM, Eun Young LEE, Eun Mi HONG
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Patent number: 7968405Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.Type: GrantFiled: February 6, 2008Date of Patent: June 28, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Mi Hong, Kwang-Tae Kim, Ji-Hoon Park
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Patent number: 7863110Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.Type: GrantFiled: October 19, 2007Date of Patent: January 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Tea-Kwang Yu, Kong-Sam Jang, Kwang-Tae Kim, Ji-Hoon Park, Eun-Mi Hong
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Publication number: 20080197401Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.Type: ApplicationFiled: February 6, 2008Publication date: August 21, 2008Inventors: Eun-Mi Hong, Kwang-Tae Kim, Ji-Hoon Park
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Publication number: 20080130367Abstract: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.Type: ApplicationFiled: February 7, 2008Publication date: June 5, 2008Inventors: Sung-Taeg Kang, Hee-Seog Jeon, Jeong-Uk Han, Chang-Hun Lee, Bo-Young Seo, Chang-Min Jeon, Eun-Mi Hong
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Publication number: 20080093701Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.Type: ApplicationFiled: October 19, 2007Publication date: April 24, 2008Inventors: Tea-Kwang Yu, Kong-Sam Jang, Kwang-Tae Kim, Ji-Hoon Park, Eun-Mi Hong
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Publication number: 20070091682Abstract: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.Type: ApplicationFiled: June 28, 2006Publication date: April 26, 2007Inventors: Sung-Taeg Kang, Hee-Seog Jeon, Jeong-Uk Han, Chang-Hun Lee, Bo-Young Seo, Chang-Min Jeon, Eun-Mi Hong