Abstract: According to aspects of the present invention, a peptide with any one sequence of SEQ ID NOS:1 to 3 exhibits high selective binding affinity to a target and the microcapsule has superior physicochemical stability. Therefore, the cosmetic composition containing the microcapsule linked to the peptide manifests high delivery efficiency of an active ingredient included in the capsule to target cells, thereby exhibiting superior skin-condition improvement effects.

Abstract: The present invention relates to a method for determining sensitivity to a simultaneous inhibitor against poly ADP ribose polymerase (PARP) and Tankyrase. According to the present invention, a colorectal treatment effect can be maximized by sorting patients having sensitivity to the simultaneous inhibitor against PARP and Tankyrase.

Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.

Abstract: A system for diagnosing and analyzing infrastructure, comprising: a storage unit storing a diagnostic script, which is for collecting system information from a target system or at least one target operating server of the target system; a script transmission unit transmitting the diagnostic script to the target system to diagnose the target system; a system information collection unit receiving the system information from the target system or the at least one target operating server as a result of the running of the diagnostic script; an analysis engine storage unit storing at least one analysis rule corresponding to the target system or the at least one target operating server; and an analysis information generation unit analyzing the system information by using the analysis rule, and generating analysis information regarding the target system and the at least one target operating server based on the results of the analyzing.

Abstract: The present invention relates to a herpes zoster vaccine composition, which comprises glycoprotein E of Varicella zoster virus, a glucopyranosyl lipid adjuvant, and a metabolic oil, and selectively increases a cell-mediated immune reaction without having disadvantages of attenuated live vaccines, thereby exhibit high safety and a high preventive effect against herpes zoster.

Abstract: Provided is an olefin-based polymer with excellent processability. The olefin-based polymer according to the present invention has a high molecular weight and a broad molecular weight distribution to show excellent processability and improved mechanical properties, thereby being usefully applied according to the intended use.

Abstract: The present invention relates to a pyrrolopyridazine derivative represented by Formula 1 of the detailed description, or a pharmaceutically acceptable salt thereof. The compound according to the present invention and a pharmaceutically acceptable salt thereof can inhibit the activity of protein kinase(s), and thus are useful for preventing or treating diseases related thereto.

Abstract: The present invention relates to a pyrrolopyridazine derivative represented by Formula 1 of the detailed description, or a pharmaceutically acceptable salt thereof. The compound according to the present invention and a pharmaceutically acceptable salt thereof can inhibit the activity of protein kinase(s), and thus are useful for preventing or treating diseases related thereto.

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.

Abstract: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.