Abstract: A method and apparatus for booting a microprocessor system using a serial (e.g., NAND-type) flash memory array having a random-access (parallel, e.g., NOR-flash type) interface. The method includes loading a boot code loader stored in the serial (e.g., NAND-type) flash memory array into a RAM when power is turned on, according to a routine of a read-only memory (ROM) of the microprocessor; loading boot code stored in the serial flash memory into an internal or external (main) RAM of the microprocessor according to the boot code loader; loading application code stored in the serial flash memory into the main (RAM) memory according to the boot code; and executing the application code. The system may be manufactured at a low cost compared to NOR-Flash based systems, while ensuring flexibility of a microprocessor.

Abstract: A method and apparatus for booting a microprocessor system using a serial (e.g., NAND-type) flash memory array having a random-access (parallel, e.g., NOR-flash type) interface. The method includes loading a boot code loader stored in the serial (e.g., NAND-type) flash memory array into a RAM when power is turned on, according to a routine of a read-only memory (ROM) of the microprocessor; loading boot code stored in the serial flash memory into an internal or external (main) RAM of the microprocessor according to the boot code loader; loading application code stored in the serial flash memory into the main (RAM) memory according to the boot is code; and executing the application code. The system may be manufactured at a low cost compared to NOR-Flash based systems, while ensuring flexibility of a microprocessor.

Abstract: A semiconductor integrated circuit satisfying the IEEE 1149.1 standard and allowing all test access port (TAP) cores embedded in a chip to be tested on a circuit board as well as on a chip is provided. The semiconductor integrated circuit includes a plurality of TAP cores sharing a test data input pin, a test mode selection signal input pin, a test reset signal input pin, and a test clock signal input pin. An input port of a boundary scan register circuit is connected to the test data input pin. Input ports of a selection signal generating circuit are connected to the test data input pin, the test reset signal input pin, and the test clock signal input pin. The selection signal generating circuit generates selection signals for selecting one of the plurality of TAP cores and the boundary scan register circuit in response to signals input through these input pins.

Abstract: Functional blocks of an integrated circuit are tested in real time using a restricted number of output pins. The apparatus of the invention comprises an integrated circuit including a plurality of functional blocks, each of which, in response to a given stimulus, generates a similar output. The apparatus includes: a comparator for comparing the levels of like output signals from each of the functional blocks and for outputting the comparison result; a transmitter for external transmission of one of the output signals in response to the comparison result; and a failure discriminator for comparing the transmitted output signal level to a predetermined target output signal level, and if similar, transmitting a positive test result signal.

Abstract: A semiconductor integrated circuit satisfying the IEEE 1149.1 standard and allowing all test access port (TAP) cores embedded in a chip to be tested on a circuit board as well as on a chip is provided. The semiconductor integrated circuit includes a plurality of TAP cores sharing a test data input pin, a test mode selection signal input pin, a test reset signal input pin, and a test clock signal input pin. An input port of a boundary scan register circuit is connected to the test data input pin. Input ports of a selection signal generating circuit are connected to the test data input pin, the test reset signal input pin, and the test clock signal input pin. The selection signal generating circuit generates selection signals for selecting one of the plurality of TAP cores and the boundary scan register circuit in response to signals input through these input pins.