Abstract: A switched capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of the differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives the first input, and holds the received first input based on the second reference voltage. The second replica sampler circuit receives the second input, and holds the received second input based on the first reference voltage.

Abstract: The present disclosure relates to an aligning method for dual camera module, the method having: a step of fixating a first camera module in a space inside a housing; a step of inserting a second camera module by moving the second camera module into the space inside the housing; a step of aligning the second camera module by aligning a position of the second camera module with reference to a position where the first camera module is fixated; and a step of fixating the second camera module in the space inside the housing. Accordingly, more particularly, it is possible to align the two camera modules with more convenience and accuracy.

Abstract: A resonator oscillator that may be included in a gas sensing system may include an oscillator that may be electrically connected to an external resonator through a conductive line. The oscillator may generate an oscillating signal having a frequency corresponding to a resonance frequency of the external resonator in an oscillating path. A spurious resonance removal circuit on the oscillating path may remove spurious resonance caused by the conductive line from the oscillating path. A gas sensing system may include the oscillator, a resonator that includes a sensor configured to sense a gas, and a frequency counting logic that receives the oscillating signal and a reference clock signal, performs a counting operation on the oscillating signal according to a logic state of the reference clock signal to generate a counted value, and generate a gas sensing output indicating a sensed gas based on the counted value.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a ring oscillator configured to determine a frequency based on a sampling clock signal and a first control code, and generate an output clock signal having the determined frequency. The SAR ADC further includes a controller configured to generate the first control code based on a count value indicating a number of times of toggling the output clock signal.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a ring oscillator configured to determine a frequency based on a sampling clock signal and a first control code, and generate an output clock signal having the determined frequency. The SAR ADC further includes a controller configured to generate the first control code based on a count value indicating a number of times of toggling the output clock signal.

Abstract: A sample-and-hold circuit including an operational amplifier configured to output a result signal to the ADC; a feedback capacitor connected between an input terminal and an output terminal of the operational amplifier to form a feedback path; a plurality of sampling capacitor blocks each connected to one of a plurality of channels and configured to sample and hold an analog signal input to each of the channels; a plurality of controllers each connected between one of the sampling capacitor blocks and the operational amplifier; and a reset unit connected between a reference voltage source and the input terminal of the operational amplifier to reset the operational amplifier when the operational amplifier does not perform a holding operation. The plurality of controllers configured to switch the sampled signal so that held signals for the respective channels are sequentially input to the operational amplifier.

Abstract: A sample-and-hold circuit connected to an analog-to-digital converter (ADC) is provided. The sample-and-hold circuit includes an operational amplifier configured to output a result signal to the ADC; a feedback capacitor connected between an input terminal and an output terminal of the operational amplifier to form a feedback path; a plurality of sampling capacitor blocks each connected to one of a plurality of channels. The plurality of sampling capacitor blocks configured to sample and hold an analog signal input to each of the channels; a plurality of controllers each connected between one of the sampling capacitor blocks and the operational amplifier.

Abstract: An analog-to-digital conversion circuit includes a plurality of comparators and an averaging circuit. The averaging circuit is configured so that a length of a metal routing connected between output terminals of two comparators arranged on a leftmost side from among the plurality of comparators or a length of a metal routing connected between output terminals of two comparators arranged on a rightmost side from among the plurality of comparators is less than a length of a metal routing connected between output terminals of two comparators to which reference voltages having levels that are closest in magnitude are input.

Abstract: A multistage amplifying circuit includes a first amplifying circuit that either samples a first analog voltage input or amplifies a difference between the first analog voltage and a first digital voltage converted from the first analog voltage, in response to a control signal. A second amplifying circuit either samples a second analog voltage input or amplifies a difference between the second analog voltage and a second digital voltage converted from the second analog voltage, in response to the control signal. A common amplifier receives output voltages of the first amplifying circuit and the second amplifying circuit and either resets the output voltage of the first amplifying circuit and determines an output voltage by using the second amplifying circuit, or resets the output voltage of the second amplifying circuit and determines an output voltage by using the first amplifying circuit, in response to the control signal.

Abstract: An analog-to-digital converter includes a first logic unit and a second logic unit. The first logic unit is configured to receive a plurality of thermometer codes and inverse thermometer codes generated based on an analog signal received by the analog-to-digital converter and to generate a plurality of first digital codes that periodically repeat the same pattern based on a transition position of a logic value in each of the thermometer codes and the inverse thermometer codes. The second logic unit is configured to receive the plurality of first digital codes and to generate a plurality of second digital codes based on logic values of a plurality of bits among all bits of each of the first digital codes.

Abstract: A multistage amplifying circuit includes a first amplifying circuit that either samples a first analog voltage input or amplifies a difference between the first analog voltage and a first digital voltage converted from the first analog voltage, in response to a control signal. A second amplifying circuit either samples a second analog voltage input or amplifies a difference between the second analog voltage and a second digital voltage converted from the second analog voltage, in response to the control signal. A common amplifier receives output voltages of the first amplifying circuit and the second amplifying circuit and either resets the output voltage of the first amplifying circuit and determines an output voltage by using the second amplifying circuit, or resets the output voltage of the second amplifying circuit and determines an output voltage by using the first amplifying circuit, in response to the control signal.

Abstract: An analog-to-digital conversion circuit includes a plurality of comparators and an averaging circuit. The averaging circuit is configured so that a length of a metal routing connected between output terminals of two comparators arranged on a leftmost side from among the plurality of comparators or a length of a metal routing connected between output terminals of two comparators arranged on a rightmost side from among the plurality of comparators is less than a length of a metal routing connected between output terminals of two comparators to which reference voltages having levels that are closest in magnitude are input.

Abstract: An analog-to-digital converter includes a first logic unit and a second logic unit. The first logic unit is configured to receive a plurality of thermometer codes and inverse thermometer codes generated based on an analog signal received by the analog-to-digital converter and to generate a plurality of first digital codes that periodically repeat the same pattern based on a transition position of a logic value in each of the thermometer codes and the inverse thermometer codes. The second logic unit is configured to receive the plurality of first digital codes and to generate a plurality of second digital codes based on logic values of a plurality of bits among all bits of each of the first digital codes.

Abstract: A low-voltage operational amplifier includes a differential amplifying stage, an output amplifying stage and a compensation stage. The differential amplifying stage amplifies a difference between a first signal and a second signal that constitute a differential pair using an input pair of NMOS transistors, and outputs an amplified first signal and an amplified second signal. The output amplifying stage amplifies a difference between the amplified first signal and the amplified second signal using an input pair of PMOS transistors, and outputs a first output signal and a second output signal that constitute a differential pair. The compensation stage receives the amplified first signal, the amplified second signal, the first output signal, and the second output signal, and reduces a settling time of the first output signal and the second output signal.

Abstract: In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.

Abstract: A low-voltage operational amplifier includes a differential amplifying stage, an output amplifying stage and a compensation stage. The differential amplifying stage amplifies a difference between a first signal and a second signal that constitute a differential pair using an input pair of NMOS transistors, and outputs an amplified first signal and an amplified second signal. The output amplifying stage amplifies a difference between the amplified first signal and the amplified second signal using an input pair of PMOS transistors, and outputs a first output signal and a second output signal that constitute a differential pair. The compensation stage receives the amplified first signal, the amplified second signal, the first output signal, and the second output signal, and reduces a settling time of the first output signal and the second output signal.

Abstract: In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.