Patents by Inventor Eunseok Song
Eunseok Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136329Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.Type: ApplicationFiled: December 29, 2023Publication date: April 25, 2024Inventors: Hyuekjae Lee, Dae-Woo Kim, Eunseok Song
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Publication number: 20240088118Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Manho LEE, Eunseok SONG, Keung Beum KIM, Kyung Suk OH, Eon Soo JANG
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Publication number: 20240071943Abstract: A semiconductor package includes a substrate having a cavity, a bridge chip structure in the cavity of the substrate and including a first bridge chip and a second bridge chip stacked on the first bridge chip, and a plurality of semiconductor chips spaced apart laterally on the substrate. Each of the plurality of semiconductor chips includes a first region that is electrically connected to the first bridge chip and a second region that is electrically connected to the second bridge chip.Type: ApplicationFiled: August 25, 2023Publication date: February 29, 2024Inventor: Eunseok Song
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Patent number: 11901336Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.Type: GrantFiled: June 23, 2021Date of Patent: February 13, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuekjae Lee, Dae-woo Kim, Eunseok Song
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Patent number: 11887965Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip, an insulating layer surrounding the first and second semiconductor chips on the first redistribution substrate, a second redistribution substrate disposed on the second semiconductor chip and on which the second semiconductor chip is mounted, and a connection terminal disposed at a side of the first and second semiconductor chips and connected to the first and second redistribution substrates. An inactive surface of the second semiconductor chip is in contact with an inactive surface of the first semiconductor chip. At an interface of the first and second semiconductor chips, an upper portion of the first semiconductor chip and a lower portion of the second semiconductor chip constitute one body formed of a same material.Type: GrantFiled: January 22, 2021Date of Patent: January 30, 2024Inventors: Eunseok Song, Kyung Suk Oh
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Patent number: 11862618Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.Type: GrantFiled: July 7, 2021Date of Patent: January 2, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Manho Lee, Eunseok Song, Keung Beum Kim, Kyung Suk Oh, Eon Soo Jang
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Patent number: 11837577Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.Type: GrantFiled: June 29, 2022Date of Patent: December 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ae-Nee Jang, Kyung Suk Oh, Eunseok Song, Seung-Yong Cha
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Publication number: 20230223390Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.Type: ApplicationFiled: March 15, 2023Publication date: July 13, 2023Inventors: Manho Lee, Eunseok Song, Kyungsuk Oh, Seonghwan Jeon
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Patent number: 11631660Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.Type: GrantFiled: April 28, 2021Date of Patent: April 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Manho Lee, Eunseok Song, Kyungsuk Oh, Seonghwan Jeon
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Publication number: 20230101041Abstract: A three-dimensional (3D) laminated chip that includes a first semiconductor chip including a first through electrode disposed therein. A second semiconductor chip is arranged horizontally adjacent to the first semiconductor chip. A third semiconductor chip is arranged on the first semiconductor chip and the second semiconductor chip. A size of the third semiconductor chip is greater than a size of the first semiconductor chip.Type: ApplicationFiled: May 13, 2022Publication date: March 30, 2023Inventor: Eunseok SONG
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Publication number: 20230099787Abstract: A semiconductor package includes a substrate, a die stack on the substrate, and connection terminals between the substrate and the die stack. The die stack includes a first die having a first active surface facing the substrate, the first die including first through electrodes vertically penetrating the first die, a second die on the first die and having a second active surface, the second die including second through electrodes vertically penetrating the second die, and a third die on the second die and having a third active surface facing the substrate. The second active surface of the second die is in direct contact with one of the first or third active surfaces.Type: ApplicationFiled: December 2, 2022Publication date: March 30, 2023Inventors: Eunseok Song, Kyung Suk Oh
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Publication number: 20230057342Abstract: A semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulating circuit that regulates a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.Type: ApplicationFiled: October 21, 2022Publication date: February 23, 2023Inventors: EUNSEOK SONG, Kyungsuk Oh, Seho You
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Publication number: 20220415775Abstract: A semiconductor package is disclosed. The semiconductor package may include a package substrate, an upper semiconductor chip on the package substrate, and a lower semiconductor chip between the package substrate and the upper semiconductor chip. The upper semiconductor chip may include a core region having a power circuit thereon and a logic cell region having a logic circuit thereon. The lower semiconductor chip may include a power wire region vertically overlapping the core region. The lower semiconductor chip may include a first substrate, a first through electrode, and a second through electrode, the first substrate including an active surface having an integrated circuit thereon, and a first through electrode and a second through electrode penetrating the first substrate in the power wire region. A distance between the first and second through electrodes may be smaller than a width of the first through electrode.Type: ApplicationFiled: March 7, 2022Publication date: December 29, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Eunseok SONG, Kyung Suk OH
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Patent number: 11532591Abstract: A semiconductor package includes a substrate, a die stack on the substrate, and connection terminals between the substrate and the die stack. The die stack includes a first die having a first active surface facing the substrate, the first die including first through electrodes vertically penetrating the first die, a second die on the first die and having a second active surface, the second die including second through electrodes vertically penetrating the second die, and a third die on the second die and having a third active surface facing the substrate. The second active surface of the second die is in direct contact with one of the first or third active surfaces.Type: GrantFiled: July 31, 2020Date of Patent: December 20, 2022Inventors: Eunseok Song, Kyung Suk Oh
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Publication number: 20220352128Abstract: A semiconductor package includes a lower redistribution layer, a lower semiconductor chip and a plurality of conductive connection structures attached to the lower redistribution layer. An upper redistribution layer is disposed on the lower semiconductor chip and the plurality of conductive connection structures. An upper semiconductor chip has an active plane corresponding to an active plane of the lower semiconductor chip and is disposed on the upper redistribution layer. The lower semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first substrate. An upper wiring structure is disposed on the first surface of the semiconductor substrate. A buried power rail fills a portion of a buried rail hole extending from the first surface toward the second surface. A through electrode fills a through hole extending from the second surface toward the first surface.Type: ApplicationFiled: January 21, 2022Publication date: November 3, 2022Inventors: Manho Lee, Eunseok Song, Kyungsuk Oh
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Patent number: 11482516Abstract: A semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulating circuit that regulates a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.Type: GrantFiled: August 26, 2020Date of Patent: October 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eunseok Song, Kyungsuk Oh, Seho You
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Publication number: 20220328454Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ae-Nee JANG, Kyung Suk OH, Eunseok SONG, Seung-Yong CHA
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Patent number: 11398454Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.Type: GrantFiled: May 26, 2020Date of Patent: July 26, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ae-Nee Jang, Kyung Suk Oh, Eunseok Song, Seung-Yong Cha
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Publication number: 20220165721Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.Type: ApplicationFiled: July 7, 2021Publication date: May 26, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Manho LEE, Eunseok SONG, Keung Beum KIM, Kyung Suk OH, Eon Soo JANG
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Publication number: 20220139880Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.Type: ApplicationFiled: June 23, 2021Publication date: May 5, 2022Inventors: Hyuekjae Lee, Dae-woo Kim, Eunseok Song