Patents by Inventor Eun-Sil Kim
Eun-Sil Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957669Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.Type: GrantFiled: August 10, 2018Date of Patent: April 16, 2024Assignee: AMOREPACIFIC CORPORATIONInventors: Joon Ho Choi, Won Kyung Cho, Kwang-Hyun Shin, Byoung Young Woo, Ki-Wha Lee, Min-Soo Kim, Jong Hwa Roh, Mi Young Park, Young-Ho Park, Eun Sil Park, Jae Hong Park
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Patent number: 11928998Abstract: A display device includes a display panel including a first partial panel region and a second partial panel region, and a panel driver which drives the display panel. The panel driver determines a first driving frequency for the first partial panel region and a second driving frequency for the second partial panel region. In a case where the first driving frequency and the second driving frequency are different from each other, the panel driver sets a boundary portion including a boundary between the first partial panel region and the second partial panel region, and determines a third driving frequency for the boundary portion to be between the first driving frequency and the second driving frequency.Type: GrantFiled: February 13, 2023Date of Patent: March 12, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Sangan Kwon, Soon-Dong Kim, Taehoon Kim, Hui Nam, Eun Sil Yun, Changnoh Yoon
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Patent number: 11917755Abstract: The carrier-foil-attached ultra-thin copper foil according to one embodiment of the present invention comprises a carrier foil, a release layer, a first ultra-thin copper foil, a Cu—Al bonding strength improvement layer, an Al layer, and a second ultra-thin copper foil, wherein the release layer may comprise a first metal (A3) having peeling properties, and a second metal (B3) and third metal (C3) facilitating the plating of the first metal (A3).Type: GrantFiled: January 15, 2018Date of Patent: February 27, 2024Assignee: Lotte Energy Materials CorporationInventors: Won Jin Beom, Sun Hyung Lee, Eun Sil Choi, Ki Deok Song, Hyung Cheol Kim
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Patent number: 11195790Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.Type: GrantFiled: November 15, 2019Date of Patent: December 7, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Akihisa Kuroyanagi, Jun Woo Myung, Eun Sil Kim, Yeong A Kim
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Patent number: 10854528Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed on side surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.Type: GrantFiled: January 17, 2020Date of Patent: December 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Woo Myung, Akihisa Kuroyanagi, Yeong A Kim, Eun Sil Kim
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Publication number: 20200152538Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.Type: ApplicationFiled: January 17, 2020Publication date: May 14, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Woo MYUNG, Akihisa KUROYANAGI, Yeong A. KIM, Eun Sil KIM
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Publication number: 20200083163Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.Type: ApplicationFiled: November 15, 2019Publication date: March 12, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Akihisa KUROYANAGI, Jun Woo MYUNG, Eun Sil KIM, Yeong A KIM
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Patent number: 10541187Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.Type: GrantFiled: April 11, 2018Date of Patent: January 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Woo Myung, Akihisa Kuroyanagi, Yeong A Kim, Eun Sil Kim
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Patent number: 10504836Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.Type: GrantFiled: August 2, 2018Date of Patent: December 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Akihisa Kuroyanagi, Jun Woo Myung, Eun Sil Kim, Yeong A Kim
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Patent number: 10475776Abstract: A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.Type: GrantFiled: February 20, 2018Date of Patent: November 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeong A Kim, Eun Sil Kim, Young Gwan Ko, Akihisa Kuroyanagi, Jin Su Kim, Jun Woo Myung
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Patent number: 10467450Abstract: A fan-out sensor package includes: a core member including a wiring layer including a plurality of layers and having a through-hole; an integrated circuit (IC) for a sensor disposed in the through-hole; an encapsulant encapsulating at least portions of the core member and the IC for a sensor; and a connection member disposed on the core member and the IC for a sensor and including a plurality of circuit layers, wherein the circuit layer includes sensing patterns detecting a change in capacitance.Type: GrantFiled: April 30, 2018Date of Patent: November 5, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ju Ho Kim, Eun Sil Kim, Sang Kyu Lee, Jong Man Kim, Seok Hwan Kim
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Publication number: 20190252311Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.Type: ApplicationFiled: August 2, 2018Publication date: August 15, 2019Inventors: Akihisa KUROYANAGI, Jun Woo MYUNG, Eun Sil KIM, Yeong A KIM
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Publication number: 20190163945Abstract: A fan-out sensor package includes: a core member including a wiring layer including a plurality of layers and having a through-hole; an integrated circuit (IC) for a sensor disposed in the through-hole; an encapsulant encapsulating at least portions of the core member and the IC for a sensor; and a connection member disposed on the core member and the IC for a sensor and including a plurality of circuit layers, wherein the circuit layer includes sensing patterns detecting a change in capacitance.Type: ApplicationFiled: April 30, 2018Publication date: May 30, 2019Inventors: Ju Ho KIM, Eun Sil KIM, Sang Kyu LEE, Jong Man KIM, Seok Hwan KIM
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Publication number: 20190139851Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.Type: ApplicationFiled: April 11, 2018Publication date: May 9, 2019Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jun Woo MYUNG, Akihisa KUROYANAGI, Yeong A KIM, Eun Sil KIM
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Publication number: 20190131285Abstract: A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.Type: ApplicationFiled: February 20, 2018Publication date: May 2, 2019Inventors: Yeong A KIM, Eun Sil KIM, Young Gwan KO, Akihisa KUROYANAGI, Jin Su KIM, Jun Woo MYUNG
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Patent number: 10276467Abstract: A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.Type: GrantFiled: February 23, 2017Date of Patent: April 30, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Eun Sil Kim, Doo Hwan Lee, Dae Jung Byun, Tae Ho Ko, Yeong A Kim
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Publication number: 20170278766Abstract: A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.Type: ApplicationFiled: February 23, 2017Publication date: September 28, 2017Inventors: Eun Sil KIM, Doo Hwan LEE, Dae Jung BYUN, Tae Ho KO, Yeong A. KIM
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Publication number: 20170086292Abstract: A prepreg includes a core layer, a first resin layer including a first resin material and laminated on a first side of the core layer, the first resin material impregnating a portion of the core layer, and a second resin layer including a second resin material and laminated on a second side of the core layer, the second resin material impregnating a portion of the core layer so as to form a non-linear joint interface with the first resin material.Type: ApplicationFiled: July 5, 2016Publication date: March 23, 2017Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Eun-Sil KIM, Keun-Yong LEE, Seong-Hyun YOO, Sang-Hyun SHIN, Jin-Ho HONG
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Publication number: 20160135294Abstract: A prepreg includes: a core material having a first resin material impregnated therein; and second resin materials laminated above and below the core material and including a non-linear joint interface formed with the first resin material.Type: ApplicationFiled: November 4, 2015Publication date: May 12, 2016Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Eun-Sil KIM, Sang-Hyun SHIN
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Patent number: 9288902Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes a light-blocking glass substrate; a negative photosensitive insulating layer formed on the glass substrate; and a circuit pattern formed on the glass substrate and embedded in the negative photosensitive insulating layer.Type: GrantFiled: December 4, 2013Date of Patent: March 15, 2016Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Eun Sil Kim, Sung Han Kim, Sa Yong Lee, Jin Ho Hong, Yong Il Kwon, Sang Hyun Shin, Keun Yong Lee