Patents by Inventor Eun-Sub Lee

Eun-Sub Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153095
    Abstract: A side outer extraction method may include receiving, by at least one processor, an image, of a vehicle, preprocessed from three-dimensional (3D) data from a computer-aided design (CAD) module, detecting, using an artificial intelligence model, a classification value and a bounding box for each region, of a plurality of regions, corresponding to one of a plurality of target references of the preprocessed image, transmitting, to the CAD module, a signal indicating the classification value and the bounding box for each region of the plurality of regions, and causing extraction, by the CAD module, of the plurality of target references from the classification value and the bounding box for each region of the plurality of regions, based on the received signal.
    Type: Application
    Filed: August 7, 2023
    Publication date: May 9, 2024
    Inventors: SungHyun Park, Sang Hwan Jun, Jee-Hyong Lee, Eun-Ho Lee, Tae-Hyun Kim, Jin Sub Lee
  • Patent number: 11979677
    Abstract: An image sensor is provided. The image sensor includes: a pixel array including a plurality of pixels arranged along rows and columns; and a row driver which drives the plurality of pixels for each of the rows, wherein each of the plurality of pixels includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a plurality of photoelectric conversion elements sharing a floating diffusion area with each other, and a micro lens disposed to overlap the plurality of photoelectric conversion elements, a readout area is defined on the pixel array in accordance with a preset readout mode, and the row driver generates a drive signal for reading out signals provided from a photoelectric conversion element included in the readout area from among the plurality of photoelectric conversion elements, and provides the drive signal to the pixel array.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: May 7, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Sub Shim, Kyung Ho Lee
  • Patent number: 11957141
    Abstract: An apparatus and method for manufacturing a grilled seaweed includes the apparatus comprising a grilling unit having a first housing with a first inlet opening and a first outlet opening which communicate with each other; a first conveyor for transferring a sheet of seaweed from the first inlet opening to the first outlet opening; a first heating source installed over the first conveyor to discharge a flame onto a top surface of the seaweed being transferred by the first conveyor; and a second heating source installed on both sides of a lower portion of the first conveyor to apply a flame onto a bottom surface of the seaweed being transferred by the first conveyor.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 16, 2024
    Assignees: CJ CHEILJEDANG CORPORATION, CJ SEAFOOD CORPORATION
    Inventors: Joo Dong Park, Chang Yong Lee, Eun Soo Kwak, Dae Ik Kang, Tae Hyeong Kim, Young Sub Choi
  • Patent number: 11947928
    Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: April 2, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Craig Warner, Eun Sub Lee, Sai Rahul Chalamalasetti, Martin Foltin
  • Publication number: 20220092393
    Abstract: Systems and methods are provided to improve traditional chip processing. Using crossbar computations, the convolution layer can be flattened into vectors, and the vectors can be grouped into a matrix where each row or column is a flattened filter. Each submatrix of the input corresponding to a position of a convolution window is also flattened into a vector. The convolution is computed as the dot product of each input vector and the filter matrix. Using intra-crossbar computations, the unused space of the crossbars is used to store replicas of the filters matrices and the unused space in XIN is used to store more elements of the input. In inter-crossbar computations, the unused crossbars are used to store replicas of the filters matrices and the unused XINs are used to store more elements of the input. Then, the method performs multiple convolution iterations in a single step.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Inventors: GLAUCIMAR DA SIKVA AGUIAR, FRANCISCO PLÍNIO OLIVEIRA SILVEIRA, EUN SUB LEE, RODRIGO JOSE DA ROSA ANTUNES, JOAQUIM GOMES DA COSTA EULALIO DE SOUZA, MARTIN FOLTIN, JEFFERSON RODRIGO ALVES CAVALCANTE, LUCAS LEITE, ARTHUR CARVALHO WALRAVEN DA CUNHA, MONYCKY VASCONCELOS FRAZAO, ALEX FERREIRA RAMIRES TRAJANO
  • Publication number: 20220075597
    Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 10, 2022
    Inventors: Craig Warner, Eun Sub Lee, Sai Rahul Chalamalasetti, Martin Foltin
  • Publication number: 20210110243
    Abstract: Systems are methods are provided for implementing a deep learning accelerator system interface (DLASI). The DLASI connects an accelerator having a plurality of inference computation units to a memory of the host computer system during an inference operation. The DLASI allows interoperability between a main memory of a host computer, which uses 64 B cache lines, for example, and inference computation units, such as tiles, which are designed with smaller on-die memory using 16-bit words. The DLASI can include several components that function collectively to provide the interface between the server memory and a plurality of tiles. For example, the DLASI can include: a switch connected to the plurality of tiles; a host interface; a bridge connected to the switch and the host interface; and a deep learning accelerator fabric protocol. The fabric protocol can also implement a pipelining scheme which optimizes throughput of the multiple tiles of the accelerator.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 15, 2021
    Inventors: CRAIG WARNER, Chris Michael Brueggen, Eun Sub Lee
  • Patent number: 7422436
    Abstract: A slide module having a first slide member moving in a lengthwise direction, a second slide member moving in a widthwise direction, and a guide member disposed between the first and second slide members, guiding movement of the first slide member in the lengthwise direction and guiding movement of the second slide member in the widthwise direction. Accordingly, when the slide module is moved in the lengthwise direction, its movement in the widthwise direction is limited, while when the slide module is moved in the widthwise direction, its movement in the lengthwise direction is limited. A mobile terminal having the slide module is capable opening in the lengthwise direction and the widthwise direction.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: September 9, 2008
    Assignee: LG Electronics Inc.
    Inventor: Eun-Sub Lee
  • Publication number: 20070082545
    Abstract: A slide module having a first slide member moving in a lengthwise direction, a second slide member moving in a widthwise direction, and a guide member disposed between the first and second slide members, guiding movement of the first slide member in the lengthwise direction and guiding movement of the second slide member in the widthwise direction. Accordingly, when the slide module is moved in the lengthwise direction, its movement in the widthwise direction is limited, while when the slide module is moved in the widthwise direction, its movement in the lengthwise direction is limited. A mobile terminal having the slide module is capable opening in the lengthwise direction and the widthwise direction.
    Type: Application
    Filed: October 12, 2006
    Publication date: April 12, 2007
    Inventor: Eun-Sub Lee
  • Patent number: 5813271
    Abstract: A method of manufacturing a frame for cathode ray tubes includes the steps of blanking a workpiece while keeping junctions thereon and punching a transformable area of the workpiece to form pilot holes thereon, piercing the blanked portion into a TV or monitor screen shape, forming the edge of the screen-shape portion such that it bends inward, and drawing the formed portion to be molded into a frame while notching the junctions. The steps are performed in one press simultaneously or sequentially.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: September 29, 1998
    Assignee: Orion Metal Company Ltd.
    Inventors: Eun Sub Lee, Kyung Yul An