Patents by Inventor Eun Suk Hong

Eun Suk Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6573176
    Abstract: A method of forming a dual damascene line structure suitable for forming a fine pattern is disclosed in the present invention. The method for forming a dual damascene line structure on a substrate includes sequentially depositing an inter-metal dielectric and a first hard mask over the substrate, partially removing the first hard mask to have a positive trench pattern using a first photoresist pattern as a mask, forming a second hard mask having a substantially different etch selectivity from the first hard mask on the partially removed portion of the first hard mask, selectively removing the first hard mask to have a negative via hole pattern using a second photoresist pattern as a mask, partially removing the inter-metal dielectric to have a via hole pattern using the first hard mask as a mask, and forming a trench and a via hole by removing the exposed first hard mask and selectively etching the inter-metal dielectric using the second hard mask.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: June 3, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun Suk Hong
  • Publication number: 20030003715
    Abstract: A method of forming a dual damascene line structure suitable for forming a fine pattern is disclosed in the present invention. The method for forming a dual damascene line structure on a substrate includes sequentially depositing an inter-metal dielectric and a first hard mask over the substrate, partially removing the first hard mask to have a positive trench pattern using a first photoresist pattern as a mask, forming a second hard mask having a substantially different etch selectivity from the first hard mask on the partially removed portion of the first hard mask, selectively removing the first hard mask to have a negative via hole pattern using a second photoresist pattern as a mask, partially removing the inter-metal dielectric to have a via hole pattern using the first hard mask as a mask, and forming a trench and a via hole by removing the exposed first hard mask and selectively etching the inter-metal dielectric using the second hard mask.
    Type: Application
    Filed: February 5, 2002
    Publication date: January 2, 2003
    Applicant: Hynix Semiconductor Inc.
    Inventor: Eun Suk Hong