Patents by Inventor Eun Suk Lee
Eun Suk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967267Abstract: Provided is a display device including a display panel, an optical sensor, a timing controller, a scan driver, a data driver, and an image controller. The timing controller controls an image refresh rate of the display panel based on a refresh rate control signal. Thus, the display device provides improved visibility.Type: GrantFiled: May 2, 2023Date of Patent: April 23, 2024Assignees: Samsung Display Co., Ltd., UNIST (Ulsan National Institute Of Science and Technology)Inventors: Hyo Sun Kim, Oh Sang Kwon, Seong Gyu Choe, Chang Yeong Han, Min Kyung Kim, You Ra Kim, Eun Jung Lee, Hyung Suk Hwang
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Patent number: 11966919Abstract: Various example embodiments of the disclosure relate to an electronic device and a wireless communication connection control method thereof.Type: GrantFiled: March 14, 2022Date of Patent: April 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Ho Kang, Jinhyun Park, Ye-Ji Yoon, Jun-Hak Lim, Wontae Chae, Jongmu Choi, Bokun Choi, Doo-Suk Kang, Sun-Kee Lee, Moonsoo Kim, Eun Jung Hyun
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Patent number: 11961679Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes stacked in a first direction, and external electrodes, wherein the body includes an active portion, a side margin portion covering at least one of a first surface and a second surface of the active portion opposing each other in a second direction, and a cover portion covering the active portion in the first direction, respective dielectric layers among the plurality of dielectric layers include a barium titanate-based composition, the dielectric layer of the side margin portion includes Sn, and a content of Sn in the dielectric layer of the side margin portion is different from that of Sn in the dielectric layer of the active portion, and the dielectric layer of the side margin portion includes at least some grains having a core-shell structure.Type: GrantFiled: November 2, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Woo Kim, Eun Jung Lee, Jong Suk Jeong, Chun Hee Seo, Jong Hoon Yoo, Tae Hyung Kim, Ho Sam Choi, Sim Chung Kang
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Publication number: 20240101810Abstract: The present invention relates to a composition for forming a composite polymer film, a method for preparing the composition for forming a composite polymer film, a composite polymer film and a method for preparing the composite polymer film. The composition for forming a composite polymer film comprises: a fluorine-based polymer solution comprising a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the fluorine-based polymer solution. The method for preparing the composition for forming a composite polymer film comprises the steps of: preparing a fluorine-based polymer solution comprising a fluorine-based polymer; and dispersing polyvinylidene fluoride nanoparticles in the fluorine-based polymer solution. The composite polymer film comprises: a polymer matrix formed from a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the polymer matrix.Type: ApplicationFiled: September 4, 2020Publication date: March 28, 2024Applicants: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY, KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGYInventors: Eun Ho SOHN, Shin Hong YOOK, Hong Suk KANG, In Joon PARK, Sang Goo LEE, Soo Bok LEE, Won Wook SO, Hyeon Jun HEO, Dong Je HAN, Seon Woo KIM
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Patent number: 11943994Abstract: A display device and a method of manufacturing the same are provided. The display device, comprises a first base substrate, a first barrier layer disposed on the first base substrate, a second base substrate disposed on the first barrier layer, at least one transistor disposed on the second base substrate, and an organic light emitting diode disposed on the at least one transistor, wherein the first barrier layer includes a silicon oxide, and has an adhesion force of 200 gf/inch or more to the second base substrate.Type: GrantFiled: August 17, 2021Date of Patent: March 26, 2024Assignee: Samsung Display Co., Ltd.Inventors: Chul Min Bae, Eun Jin Kwak, Jin Suk Lee, Jung Yun Jo, Ji Hye Han, Young In Hwang
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Publication number: 20210401112Abstract: A method for making an article of footwear includes placing a purified recombinant resilin composition in a mold with a cross-linking solution, incubating the recombinant resilin composition in the cross-linking solution to generate a solid resilin material, fabricating a cushioning element of the article of footwear including at least a portion of the solid resilin material, and assembling the cushioning element insole with at least an upper of the article of footwear.Type: ApplicationFiled: September 9, 2021Publication date: December 30, 2021Inventors: Matthew Jordan Smith, Michael Eun-Suk Lee, Mitchell Joseph Heinrich, Paul James Jehlen
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Patent number: 11178934Abstract: An article of footwear includes an upper and a midsole coupled with the upper. The midsole includes at least a portion of a solid resilin material comprising a cross-linked recombinant resilin and a polar nonaqueous solvent.Type: GrantFiled: July 16, 2019Date of Patent: November 23, 2021Assignee: Bolt Threads Inc.Inventors: Matthew Jordan Smith, Michael Eun-Suk Lee, Mitchell Joseph Heinrich, Paul James Jehlen
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Publication number: 20200102429Abstract: Disclosed herein are improved cross-linked resilin compositions and methods of making these improved compositions. These include new methods of cross-linking resilin compositions, use of polar nonaqueous solvents for adjusting material properties of cross-linked resilin solid compositions, and resilin foam compositions and methods of making the same.Type: ApplicationFiled: July 18, 2019Publication date: April 2, 2020Inventors: Matthew Jordan Smith, Michael Eun-Suk Lee, Mitchell Joseph Heinrich, Paul James Jehlen
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Publication number: 20200022451Abstract: An article of footwear includes an upper and a midsole coupled with the upper. The midsole includes at least a portion of a solid resilin material comprising a cross-linked recombinant resilin and a polar nonaqueous solvent.Type: ApplicationFiled: July 16, 2019Publication date: January 23, 2020Inventors: Matthew Jordan Smith, Michael Eun-Suk Lee, Mitchell Joseph Heinrich, Paul James Jehlen
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Publication number: 20190296647Abstract: A device and method for controlling a power supply. The method includes: a voltage signal in a primary winding is delayed, and the delayed voltage signal is sampled and held after a time when a rectifying diode stops conducting a current, then the sampled and held signal is used as a feedback signal of the power supply. Therefore, only one sampling and holding circuit is needed, the area of the circuit can be reduced and the cost of the integrated circuit can be decreased, meanwhile regulation characteristics are not deteriorated.Type: ApplicationFiled: March 20, 2018Publication date: September 26, 2019Applicants: Sanken Electric Co., Ltd., Sanken Electric Korea Co., Ltd.Inventors: Eun Suk LEE, Masaaki SHIMADA, Mi Yong KIM, Tetsuya TABATA, Hiroaki NAKAMURA
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Patent number: 10396670Abstract: A device and method for controlling a power supply. The method includes: a first correction signal is generated according to a down-slope waveform and a second correction signal is generated according to an up-slope waveform, in a period of the switching element. Therefore, two kinds of corrections can be performed by using an oscillator, while the area of the circuit can be reduced and the cost of the integrated circuit can be decreased.Type: GrantFiled: March 22, 2018Date of Patent: August 27, 2019Assignees: Sanken Electric Co., Ltd., Sanken Electric Korea Co., Ltd.Inventors: Jung Eun Oh, Mi Yong Kim, Eun Suk Lee, Masaaki Shimada, Tetsuya Tabata, Hiroaki Nakamura
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Patent number: 10298135Abstract: A device and method for controlling a power supply. The method includes: monitoring a feedback signal of a feedback terminal; determining whether the feedback signal of the feedback terminal is not a pulse signal; and terminating an on/off operation of a switching element when the feedback signal of the feedback terminal is not a pulse signal. Therefore, an abnormal status of the device can be correctly detected with a simple structure when the feedback terminal is open or is shorted with other terminals, while an error operation and a damage of the device can be avoided.Type: GrantFiled: March 22, 2018Date of Patent: May 21, 2019Assignees: Sanken Electric Co., Ltd., Sanken Electric Korea Co., Ltd.Inventors: Mi Yong Kim, Masaaki Shimada, Eun Suk Lee, Tetsuya Tabata, Hiroaki Nakamura
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Publication number: 20120176295Abstract: Disclosed are a triple display device and a computer employing same. The triple display device of the present invention comprises a main display, a first auxiliary display, and a second auxiliary display. The main display has a first input port connected, via a first cable, to a first output port of a dual graphic card installed on a main board of a computer, to display status information of the program being run on the computer. The first auxiliary display has a second input port connected, via a second cable, to a second output port of the dual graphic card, to display data (for example, advertisement content or company intranet information) automatically executed on the computer and provided by a specific site connected via the Internet. The second auxiliary display has a USB video module which has a USB output port connected, via a third cable, to a USB output port of the main board, to display data being executed in the main board in accordance with the command inputted by a user.Type: ApplicationFiled: September 17, 2010Publication date: July 12, 2012Inventor: Eun Suk Lee
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Patent number: 7687878Abstract: A MOSFET device includes a semiconductor substrate having an active region including storage node contact forming areas and a device isolation region and having a device isolation structure which is formed in the device isolation region to delimit the active region; screening layers formed in portions of the device isolation structure on both sides of the storage node contact forming areas of the active region; a gate line including a main gate which is located in the active region and a passing gate which is located on the device isolation structure; and junction areas formed in a surface of the active region on both sides of the main gate.Type: GrantFiled: November 13, 2007Date of Patent: March 30, 2010Assignee: Hynix Semiconductor Inc.Inventor: Eun Suk Lee
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Publication number: 20080224230Abstract: A MOSFET device includes a semiconductor substrate having an active region including storage node contact forming areas and a device isolation region and having a device isolation structure which is formed in the device isolation region to delimit the active region; screening layers formed in portions of the device isolation structure on both sides of the storage node contact forming areas of the active region; a gate line including a main gate which is located in the active region and a passing gate which is located on the device isolation structure; and junction areas formed in a surface of the active region on both sides of the main gate.Type: ApplicationFiled: November 13, 2007Publication date: September 18, 2008Inventor: Eun Suk LEE
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Patent number: 7173870Abstract: Disclosed is a memory device, which combines a self-refresh enable signal and a power mode decision signal and prevents an internal voltage from being dropped down without the increase of IDD3P current when the memory device performs a self-refresh operation. The memory device includes an operation mode internal voltage generator used in an operation mode, and a controller for enabling the operation mode internal voltage generator while performing a self-refresh operation with a predetermined period and activating a memory cell array of the memory device, even when the memory device is in a stand-by mode.Type: GrantFiled: April 12, 2005Date of Patent: February 6, 2007Assignee: Hynix Semiconductor Inc.Inventor: Eun Suk Lee
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Patent number: 7045411Abstract: Disclosed are a chain gate line structure of a semiconductor device, and a method for manufacturing the same. The semiconductor device having a gate line structure comprises device isolation films formed on a semiconductor substrate for defining active regions and inactive regions; stack type gate electrodes formed on top of the active regions of the semiconductor substrate; at least one layer of an interlayer insulating film formed on the entire surface of the resultant material having the stack type gate electrodes; gate contacts formed on contact holes of the interlayer insulating film and connected to the stack type gate electrodes; and chain type gate lines for connecting the gate contacts formed in the active regions arrayed in a row among a plurality of active regions on the top of the interlayer insulating film in a concave-convex type chain structure.Type: GrantFiled: May 17, 2005Date of Patent: May 16, 2006Assignee: Hynix Semiconductor Inc.Inventor: Eun Suk Lee
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Patent number: D650779Type: GrantFiled: February 2, 2011Date of Patent: December 20, 2011Inventor: Eun-Suk Lee