Patents by Inventor Eun Suk Lee

Eun Suk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12234310
    Abstract: Disclosed is a blood-compatible polymer represented by Formula 1. A polymer obtained by grafting a fluorinated methacrylate onto a polyvinylidene fluoride copolymer and provided in one aspect of the present invention is a polymer with blood compatibility, and may provide a blood-compatible material with hydrophobicity. In addition, it is possible to provide a material with controlled contact angle and surface energy properties by controlling the hydrogen fluoride length of the fluorinated methacrylate monomer for modification. Furthermore, it is possible to provide coating with controlled surface properties and blood compatibility through a simple process. Furthermore, it is possible to provide a freestanding polymer film with blood compatibility.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: February 25, 2025
    Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOG
    Inventors: Eun Ho Sohn, Dong Je Han, Hyeon Jun Heo, Jeong Kim, In Joon Park, Jong Wook Ha, Soo Bok Lee, Hong Suk Kang, Sang Goo Lee, Shin Hong Yook
  • Publication number: 20250046814
    Abstract: A positive electrode active material for a secondary battery includes a lithium composite transition metal oxide comprising nickel (Ni), cobalt (Co), and manganese (Mn), and a coating layer formed on surfaces of the lithium composite transition metal oxide, wherein, in the lithium composite transition metal oxide, an amount of the nickel (Ni) in a total amount of transition metals is 60 mol % or more, and an amount of the manganese (Mn) is greater than an amount of the cobalt (Co), and the coating layer comprises a compound represented by Formula 1: LiaM1bOc ??[Formula 1] wherein, M1 includes aluminum (Al) and at least one selected from the group consisting of boron (B), silicon (Si), titanium (Ti), and phosphorus (P), and 1?a?4, 1?b?8, and 1?c?20.
    Type: Application
    Filed: October 25, 2024
    Publication date: February 6, 2025
    Applicant: LG Energy Solution, Ltd.
    Inventors: So Ra Baek, Min Suk Kang, Sang Wook Lee, Wang Mo Jung, Dong Hun Lee, Hye Lim Jeon, Eun Sol Lho
  • Publication number: 20240403037
    Abstract: The present disclosure according to at least one embodiment provides a software development platform, a software development platform comprising a config manager receiving config information of target software through a graphical user interface (GUI)-based config interface—the config information including config information on a plurality of items, at least some of which are for configuring a common component—, a code generator generating a code of the target software based on the config information; and an execution engine executing the generated code by using the common component in which the config information of the at least some of the items is reflected.
    Type: Application
    Filed: May 13, 2024
    Publication date: December 5, 2024
    Applicant: SAMSUNG SDS CO., LTD.
    Inventors: Geung Min HWANG, Kyoung Hee Yoon, Eun Suk Lee, Hye Mi Heo
  • Publication number: 20210401112
    Abstract: A method for making an article of footwear includes placing a purified recombinant resilin composition in a mold with a cross-linking solution, incubating the recombinant resilin composition in the cross-linking solution to generate a solid resilin material, fabricating a cushioning element of the article of footwear including at least a portion of the solid resilin material, and assembling the cushioning element insole with at least an upper of the article of footwear.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Inventors: Matthew Jordan Smith, Michael Eun-Suk Lee, Mitchell Joseph Heinrich, Paul James Jehlen
  • Patent number: 11178934
    Abstract: An article of footwear includes an upper and a midsole coupled with the upper. The midsole includes at least a portion of a solid resilin material comprising a cross-linked recombinant resilin and a polar nonaqueous solvent.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: November 23, 2021
    Assignee: Bolt Threads Inc.
    Inventors: Matthew Jordan Smith, Michael Eun-Suk Lee, Mitchell Joseph Heinrich, Paul James Jehlen
  • Publication number: 20200102429
    Abstract: Disclosed herein are improved cross-linked resilin compositions and methods of making these improved compositions. These include new methods of cross-linking resilin compositions, use of polar nonaqueous solvents for adjusting material properties of cross-linked resilin solid compositions, and resilin foam compositions and methods of making the same.
    Type: Application
    Filed: July 18, 2019
    Publication date: April 2, 2020
    Inventors: Matthew Jordan Smith, Michael Eun-Suk Lee, Mitchell Joseph Heinrich, Paul James Jehlen
  • Publication number: 20200022451
    Abstract: An article of footwear includes an upper and a midsole coupled with the upper. The midsole includes at least a portion of a solid resilin material comprising a cross-linked recombinant resilin and a polar nonaqueous solvent.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 23, 2020
    Inventors: Matthew Jordan Smith, Michael Eun-Suk Lee, Mitchell Joseph Heinrich, Paul James Jehlen
  • Publication number: 20190296647
    Abstract: A device and method for controlling a power supply. The method includes: a voltage signal in a primary winding is delayed, and the delayed voltage signal is sampled and held after a time when a rectifying diode stops conducting a current, then the sampled and held signal is used as a feedback signal of the power supply. Therefore, only one sampling and holding circuit is needed, the area of the circuit can be reduced and the cost of the integrated circuit can be decreased, meanwhile regulation characteristics are not deteriorated.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 26, 2019
    Applicants: Sanken Electric Co., Ltd., Sanken Electric Korea Co., Ltd.
    Inventors: Eun Suk LEE, Masaaki SHIMADA, Mi Yong KIM, Tetsuya TABATA, Hiroaki NAKAMURA
  • Patent number: 10396670
    Abstract: A device and method for controlling a power supply. The method includes: a first correction signal is generated according to a down-slope waveform and a second correction signal is generated according to an up-slope waveform, in a period of the switching element. Therefore, two kinds of corrections can be performed by using an oscillator, while the area of the circuit can be reduced and the cost of the integrated circuit can be decreased.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 27, 2019
    Assignees: Sanken Electric Co., Ltd., Sanken Electric Korea Co., Ltd.
    Inventors: Jung Eun Oh, Mi Yong Kim, Eun Suk Lee, Masaaki Shimada, Tetsuya Tabata, Hiroaki Nakamura
  • Patent number: 10298135
    Abstract: A device and method for controlling a power supply. The method includes: monitoring a feedback signal of a feedback terminal; determining whether the feedback signal of the feedback terminal is not a pulse signal; and terminating an on/off operation of a switching element when the feedback signal of the feedback terminal is not a pulse signal. Therefore, an abnormal status of the device can be correctly detected with a simple structure when the feedback terminal is open or is shorted with other terminals, while an error operation and a damage of the device can be avoided.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 21, 2019
    Assignees: Sanken Electric Co., Ltd., Sanken Electric Korea Co., Ltd.
    Inventors: Mi Yong Kim, Masaaki Shimada, Eun Suk Lee, Tetsuya Tabata, Hiroaki Nakamura
  • Publication number: 20120176295
    Abstract: Disclosed are a triple display device and a computer employing same. The triple display device of the present invention comprises a main display, a first auxiliary display, and a second auxiliary display. The main display has a first input port connected, via a first cable, to a first output port of a dual graphic card installed on a main board of a computer, to display status information of the program being run on the computer. The first auxiliary display has a second input port connected, via a second cable, to a second output port of the dual graphic card, to display data (for example, advertisement content or company intranet information) automatically executed on the computer and provided by a specific site connected via the Internet. The second auxiliary display has a USB video module which has a USB output port connected, via a third cable, to a USB output port of the main board, to display data being executed in the main board in accordance with the command inputted by a user.
    Type: Application
    Filed: September 17, 2010
    Publication date: July 12, 2012
    Inventor: Eun Suk Lee
  • Patent number: 7687878
    Abstract: A MOSFET device includes a semiconductor substrate having an active region including storage node contact forming areas and a device isolation region and having a device isolation structure which is formed in the device isolation region to delimit the active region; screening layers formed in portions of the device isolation structure on both sides of the storage node contact forming areas of the active region; a gate line including a main gate which is located in the active region and a passing gate which is located on the device isolation structure; and junction areas formed in a surface of the active region on both sides of the main gate.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun Suk Lee
  • Publication number: 20080224230
    Abstract: A MOSFET device includes a semiconductor substrate having an active region including storage node contact forming areas and a device isolation region and having a device isolation structure which is formed in the device isolation region to delimit the active region; screening layers formed in portions of the device isolation structure on both sides of the storage node contact forming areas of the active region; a gate line including a main gate which is located in the active region and a passing gate which is located on the device isolation structure; and junction areas formed in a surface of the active region on both sides of the main gate.
    Type: Application
    Filed: November 13, 2007
    Publication date: September 18, 2008
    Inventor: Eun Suk LEE
  • Patent number: 7173870
    Abstract: Disclosed is a memory device, which combines a self-refresh enable signal and a power mode decision signal and prevents an internal voltage from being dropped down without the increase of IDD3P current when the memory device performs a self-refresh operation. The memory device includes an operation mode internal voltage generator used in an operation mode, and a controller for enabling the operation mode internal voltage generator while performing a self-refresh operation with a predetermined period and activating a memory cell array of the memory device, even when the memory device is in a stand-by mode.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: February 6, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun Suk Lee
  • Patent number: 7045411
    Abstract: Disclosed are a chain gate line structure of a semiconductor device, and a method for manufacturing the same. The semiconductor device having a gate line structure comprises device isolation films formed on a semiconductor substrate for defining active regions and inactive regions; stack type gate electrodes formed on top of the active regions of the semiconductor substrate; at least one layer of an interlayer insulating film formed on the entire surface of the resultant material having the stack type gate electrodes; gate contacts formed on contact holes of the interlayer insulating film and connected to the stack type gate electrodes; and chain type gate lines for connecting the gate contacts formed in the active regions arrayed in a row among a plurality of active regions on the top of the interlayer insulating film in a concave-convex type chain structure.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: May 16, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun Suk Lee
  • Patent number: D650779
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: December 20, 2011
    Inventor: Eun-Suk Lee