Patents by Inventor Eun-tae Kim
Eun-tae Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10103152Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.Type: GrantFiled: June 27, 2017Date of Patent: October 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hoon Kim, Eun Tae Kim, Seong Hun Park, Youn Jae Cho, Hee Sook Park, Woong Hee Sohn, Jin Ho Oh
-
Publication number: 20180053769Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.Type: ApplicationFiled: June 27, 2017Publication date: February 22, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Hoon KIM, Eun Tae KIM, Seong Hun PARK, Youn Jae CHO, Hee Sook PARK, Woong Hee SOHN, Jin Ho OH
-
Patent number: 8993441Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.Type: GrantFiled: February 25, 2014Date of Patent: March 31, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Hyung Kim, Eun-Tae Kim, Sung-Lae Cho
-
Publication number: 20150031195Abstract: A method of fabricating a semiconductor device may include conformally forming a gate insulating layer on a substrate having a recess, conformally forming a barrier layer containing fluorine-free tungsten nitride on the substrate with the gate insulating layer using an atomic layer deposition process, and forming a gate electrode on the barrier layer to fill at least a portion of the recess.Type: ApplicationFiled: June 6, 2014Publication date: January 29, 2015Inventors: Eun Tae Kim, Jihoon Kim, Heesook Park, Jin Ho Oh, Jongmyeong Lee
-
Publication number: 20140273395Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.Type: ApplicationFiled: February 25, 2014Publication date: September 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Do-Hyung KIM, Eun-Tae KIM, Sung-Lae CHO
-
Patent number: 8548555Abstract: An active dry sensor module for measurement of bioelectricity is disclosed. The active dry sensor module of the present invention excludes the use of a conductive gel, thereby not supplying unpleasantness and discomfort to a reagent and preventing the interference of the signal due to a noise component. Further, the active dry sensor module of the present invention amplifies the biomedical signal to a desired level, thereby precisely and easily measuring the biomedical signal.Type: GrantFiled: September 14, 2012Date of Patent: October 1, 2013Assignee: NeuroSky, Inc.Inventors: Kyung-Soo Jin, Jong-Jin Lim, Jong-Gil Byeon, Eun-Tae Kim, Jin-Ho Park
-
Publication number: 20130066183Abstract: An active dry sensor module for measurement of bioelectricity is disclosed. The active dry sensor module of the present invention excludes the use of a conductive gel, thereby not supplying unpleasantness and discomfort to a reagent and preventing the interference of the signal due to a noise component. Further, the active dry sensor module of the present invention amplifies the biomedical signal to a desired level, thereby precisely and easily measuring the biomedical signal.Type: ApplicationFiled: September 14, 2012Publication date: March 14, 2013Applicant: NEUROSKY, INC.Inventors: Kyung-Soo Jin, Jong-Jin Lim, Jong-Gil Byeon, Eun-Tae Kim, Jin-Ho Park
-
Patent number: 8290563Abstract: An active dry sensor module for measurement of bioelectricity is disclosed. The active dry sensor module of the present invention excludes the use of a conductive gel, thereby not supplying unpleasantness and discomfort to a reagent and preventing the interference of the signal due to a noise component. Further, the active dry sensor module of the present invention amplifies the biomedical signal to a desired level, thereby precisely and easily measuring the biomedical signal.Type: GrantFiled: June 29, 2004Date of Patent: October 16, 2012Assignee: NeuroSky, Inc.Inventors: Kyung-Soo Jin, Jong-Jin Lim, Jong-Gil Byeon, Eun-Tae Kim, Jin-Ho Park
-
Patent number: 8090069Abstract: The present invention relates to an apparatus for generating a clock signal with jitter and a test apparatus including the same. The apparatus for generating a clock signal with jitter in accordance with the present invention includes a voltage-controlled crystal oscillator (VCXO) for generating an output signal including jitter components based on a driving power source having a specific waveform and a controlled voltage, a phase comparator for calculating a phase difference of a reference signal and the output signal, and a loop filter for generating the controlled voltage based on the phase difference calculated by the phase comparator. Accordingly, the PLL circuit unit generates a clock signal including jitter, so that the complexity and manufacturing cost of the apparatus can be reduced.Type: GrantFiled: June 19, 2008Date of Patent: January 3, 2012Assignee: Electronics and Telecommunication Research InstituteInventors: Bong Guk Yu, Eun Tae Kim, Hyung Jung Kim, Gweon Do Jo
-
Patent number: 7970021Abstract: Provided are a method and apparatus for derate matching a rate-matched data. The received data is deinterleaved and derate matched at a time, without using input buffers or constructing input buffers in parallel. Thus, a total process time necessary for the deinterleaving process and the derate matching process is reduced, and the use of memories such as the input buffers is minimized.Type: GrantFiled: August 20, 2009Date of Patent: June 28, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Eun Tae Kim, Dae Soon Cho, Hee Sang Chung, Hyeong Jun Park
-
Publication number: 20100158053Abstract: Provided are a method and apparatus for derate matching a rate-matched data. The received data is deinterleaved and derate matched at a time, without using input buffers or constructing input buffers in parallel. Thus, a total process time necessary for the deinterleaving process and the derate matching process is reduced, and the use of memories such as the input buffers is minimized.Type: ApplicationFiled: August 20, 2009Publication date: June 24, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Eun Tae KIM, Dae Soon CHO, Hee Sang CHUNG, Hyeong Jun PARK
-
Publication number: 20090316848Abstract: The present invention relates to an apparatus for generating a clock signal with jitter and a test apparatus including the same. The apparatus for generating a clock signal with jitter in accordance with the present invention includes a voltage-controlled crystal oscillator (VCXO) for generating an output signal including jitter components based on a driving power source having a specific waveform and a controlled voltage, a phase comparator for calculating a phase difference of a reference signal and the output signal, and a loop filter for generating the controlled voltage based on the phase difference calculated by the phase comparator. Accordingly, the PLL circuit unit generates a clock signal including jitter, so that the complexity and manufacturing cost of the apparatus can be reduced.Type: ApplicationFiled: June 19, 2008Publication date: December 24, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Bong Guk YU, Eun Tae Kim, Hyung Jung Kim, Gweon Do Jo
-
Publication number: 20090156925Abstract: An active dry sensor module for measurement of bioelectricity is disclosed. The active dry sensor module of the present invention excludes the use of a conductive gel, thereby not supplying unpleasantness and discomfort to a reagent and preventing the interference of the signal due to a noise component. Further, the active dry sensor module of the present invention amplifies the biomedical signal to a desired level, thereby precisely and easily measuring the biomedical signal.Type: ApplicationFiled: June 29, 2004Publication date: June 18, 2009Inventors: Kyung-Soo Jin, Jong-Jin Lim, Jong-Gil Byeon, Eun-Tae Kim, Jin-Ho Park
-
Patent number: 7307592Abstract: Disclosed is a mobile communication terminal having an ESD (electrostatic discharge) protection function that includes a multi-band intenna including: a main signal pattern line that transmits/receives a main frequency band signal and is formed in a meander-line shape; at least one sub signal pattern line that is formed unitarily with the main signal pattern line and transmits/receives a frequency band signal different from that of the main signal pattern line; a discharge pattern line that is provided between the main and sub signal pattern lines to form a spark gap and performs an ESD protection function; a feed point that is formed on the main signal pattern line for power feeding; and a shorting point that is formed on the discharge pattern line to discharge static electricity to a ground terminal.Type: GrantFiled: February 24, 2006Date of Patent: December 11, 2007Assignee: Pantech & Curitel Communications, Inc.Inventors: Book-sung Park, Eun-tae Kim
-
Publication number: 20070046550Abstract: Disclosed is a mobile communication terminal having an ESD (electrostatic discharge) protection function that includes a multi-band intenna including: a main signal pattern line that transmits/receives a main frequency band signal and is formed in a meander-line shape; at least one sub signal pattern line that is formed unitarily with the main signal pattern line and transmits/receives a frequency band signal different from that of the main signal pattern line; a discharge pattern line that is provided between the main and sub signal pattern lines to form a spark gap and performs an ESD protection function; a feed point that is formed on the main signal pattern line for power feeding; and a shorting point that is formed on the discharge pattern line to discharge static electricity to a ground terminal.Type: ApplicationFiled: February 24, 2006Publication date: March 1, 2007Inventors: Book-sung Park, Eun-tae Kim