Patents by Inventor Eun-tae Kim
Eun-tae Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974600Abstract: An aerosol generating device includes a first vaporizer configured to generate a first aerosol by heating a first liquid composition, a second vaporizer configured to generate a second aerosol by heating a second liquid composition, and a controller controlling power supplied to the first vaporizer and the second vaporizer, based on a first mode, in which a smokeless aerosol is generated, and a second mode, in which a transport amount of nicotine included in the second liquid composition is adjusted.Type: GrantFiled: December 16, 2020Date of Patent: May 7, 2024Assignee: KT&G CORPORATIONInventors: In Su Park, Sung Jong Ki, Young Joong Kim, John Tae Lee, Sun Hwan Jung, Eun Mi Jeoung
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Publication number: 20240145173Abstract: A method of manufacturing a multilayer electronic component, the method includes, attaching a margin portion green sheet including a ceramic material, a photocuring agent, and a photoinitiator to at least one end surface of each of the plurality of cut ceramic green sheet stacked bodies in the third direction, an energy irradiation operation of irradiating, with energy, the margin portion green sheet to generate a photocuring polymerization reaction between the photocuring agent and the photoinitiator.Type: ApplicationFiled: June 2, 2023Publication date: May 2, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ji Hyeon LEE, Jong Ho LEE, Eun Jung LEE, Yong Min HONG, Yong PARK, Min Woo KIM, Jung Tae PARK, Sun Mi KIM, Sim Chung KANG
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DEVICE AND METHOD FOR MEASURING SKIN CHANGES CAUSED BY BLUE LIGHT, AND BLUE LIGHT IRRADIATION DEVICE
Publication number: 20240130668Abstract: The present invention relates to a device and a method for measuring skin changes caused by blue light. A device for measuring skin changes caused by blue light according to one embodiment of the present invention comprises: at least one light source for irradiating light of a blue light band at different light amounts to a plurality of test areas set on a skin area to be tested; and a control unit for detecting a minimum pigmentation point among the test areas and calculating a light amount of the corresponding test area as a minimum pigmentation dose (MPD) for blue light. In addition, the present invention relates to a blue light irradiation device for irradiating a plurality of blue light beams in order to measure skin changes caused by blue light.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Applicant: AMOREPACIFIC CORPORATIONInventors: Hongli JO, Yuchul JUNG, Eun Joo KIM, Kyung Tae KIM, Yong Jin LEE -
Patent number: 11963610Abstract: Disclosed is a method of manufacturing bamboo toothbrush and a toothbrush manufactured thereby. According to the method of manufacturing bamboo toothbrush of a detailed embodiment of the present invention and a toothbrush manufactured by the method, it is possible to improve strength, surface roughness, and moisture resistance of a bamboo and adjust the color of the bamboo using hot pressing. Further, since sanding and polishing and separate coating and drying are not performed, the process time is reduced, whereby the manufacturing cost can be reduced.Type: GrantFiled: October 2, 2019Date of Patent: April 23, 2024Assignee: PROJECT NOAH, INC.Inventors: Kyung Tae Lee, Guen Woo Park, Eun Seob Kim
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Patent number: 11951130Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.Type: GrantFiled: March 1, 2021Date of Patent: April 9, 2024Assignee: Eutilex Co., Ltd.Inventors: Byoung S. Kwon, Young Ho Kim, Kwang Hee Kim, Ji Won Chung, Young Gyoon Chang, Bo Rim Yi, Jung Yun Lee, Seung Hyun Lee, Sun Woo Im, Jin Kyung Choi, Hyun Tae Son, Eun Hye Yoo
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Patent number: 11954891Abstract: Provided is a method of compressing an occupancy map of a three-dimensional (3D) point cloud, and more specifically, a method of compressing an occupancy map of a point cloud in which an occupancy map image of a point cloud existing in a 3D space is compressed based on a compression quality or a patch-by-patch inspection method of the occupancy map image so that compression distortion is minimized when reconstructing the compressed occupancy map image so as to remarkably improve the quality of a reconstructed occupancy map image.Type: GrantFiled: June 30, 2021Date of Patent: April 9, 2024Assignees: Electronics and Telecommunications Research Institute, IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)Inventors: Eun Young Chang, Euee Seon Jang, Tian Yu Dong, Ji Hun Cha, Kyu Tae Kim, Jae Young Ahn
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Publication number: 20240112864Abstract: A method of manufacturing a multilayer electronic component includes cutting a stack, in which internal electrode patterns and ceramic green sheets are alternately stacked in a stacking direction, to obtain unit chips and attaching a portion of a ceramic green sheet for a side margin portion to the unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet to the unit chips by compression between a first elastic body on which the ceramic green sheet is disposed and the unit chips. The first elastic body includes a first elastic layer having and a second elastic layer having an elastic modulus different from the first elastic layer, and disposed between the unit chips and the first elastic layer. An elastic modulus of the first elastic body is greater than 50 MPa and less than or equal to 1000 MPa.Type: ApplicationFiled: July 10, 2023Publication date: April 4, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong PARK, Jung Tae PARK, Jong Ho LEE, Eun Jung LEE, Yong Min HONG, Jung Jin PARK, Rak Hyeon BAEK, Sun Mi KIM, Yong Ung LEE
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Publication number: 20240071689Abstract: A method of manufacturing a multilayer electronic component includes forming a stack by stacking a plurality of ceramic green sheets on which conductive patterns are disposed on a support film, cutting the stack in a second direction, perpendicular to a first direction which is a stacking direction of the plurality of ceramic green sheets, cutting the stack in a third direction, perpendicular to the first and second directions, to obtain a plurality of unit chips, separating the unit chip from the support film, arranging the unit chip such that one of side surfaces of the unit chip is in contact with an adhesive tape, and attaching another one of the side surfaces to a ceramic green sheet for a side margin portion, and forming a side margin portion on the another one of side surfaces.Type: ApplicationFiled: March 28, 2023Publication date: February 29, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Myung Chan SON, Yong PARK, Jong Ho LEE, Eun Jung LEE, Jung Tae PARK, Min Woo KIM, Ji Hyeon LEE, Sun Mi KIM
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Patent number: 10103152Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.Type: GrantFiled: June 27, 2017Date of Patent: October 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hoon Kim, Eun Tae Kim, Seong Hun Park, Youn Jae Cho, Hee Sook Park, Woong Hee Sohn, Jin Ho Oh
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Publication number: 20180053769Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.Type: ApplicationFiled: June 27, 2017Publication date: February 22, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Hoon KIM, Eun Tae KIM, Seong Hun PARK, Youn Jae CHO, Hee Sook PARK, Woong Hee SOHN, Jin Ho OH
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Patent number: 8993441Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.Type: GrantFiled: February 25, 2014Date of Patent: March 31, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Hyung Kim, Eun-Tae Kim, Sung-Lae Cho
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Publication number: 20150031195Abstract: A method of fabricating a semiconductor device may include conformally forming a gate insulating layer on a substrate having a recess, conformally forming a barrier layer containing fluorine-free tungsten nitride on the substrate with the gate insulating layer using an atomic layer deposition process, and forming a gate electrode on the barrier layer to fill at least a portion of the recess.Type: ApplicationFiled: June 6, 2014Publication date: January 29, 2015Inventors: Eun Tae Kim, Jihoon Kim, Heesook Park, Jin Ho Oh, Jongmyeong Lee
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Publication number: 20140273395Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.Type: ApplicationFiled: February 25, 2014Publication date: September 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Do-Hyung KIM, Eun-Tae KIM, Sung-Lae CHO
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Patent number: 8548555Abstract: An active dry sensor module for measurement of bioelectricity is disclosed. The active dry sensor module of the present invention excludes the use of a conductive gel, thereby not supplying unpleasantness and discomfort to a reagent and preventing the interference of the signal due to a noise component. Further, the active dry sensor module of the present invention amplifies the biomedical signal to a desired level, thereby precisely and easily measuring the biomedical signal.Type: GrantFiled: September 14, 2012Date of Patent: October 1, 2013Assignee: NeuroSky, Inc.Inventors: Kyung-Soo Jin, Jong-Jin Lim, Jong-Gil Byeon, Eun-Tae Kim, Jin-Ho Park
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Publication number: 20130066183Abstract: An active dry sensor module for measurement of bioelectricity is disclosed. The active dry sensor module of the present invention excludes the use of a conductive gel, thereby not supplying unpleasantness and discomfort to a reagent and preventing the interference of the signal due to a noise component. Further, the active dry sensor module of the present invention amplifies the biomedical signal to a desired level, thereby precisely and easily measuring the biomedical signal.Type: ApplicationFiled: September 14, 2012Publication date: March 14, 2013Applicant: NEUROSKY, INC.Inventors: Kyung-Soo Jin, Jong-Jin Lim, Jong-Gil Byeon, Eun-Tae Kim, Jin-Ho Park
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Patent number: 8290563Abstract: An active dry sensor module for measurement of bioelectricity is disclosed. The active dry sensor module of the present invention excludes the use of a conductive gel, thereby not supplying unpleasantness and discomfort to a reagent and preventing the interference of the signal due to a noise component. Further, the active dry sensor module of the present invention amplifies the biomedical signal to a desired level, thereby precisely and easily measuring the biomedical signal.Type: GrantFiled: June 29, 2004Date of Patent: October 16, 2012Assignee: NeuroSky, Inc.Inventors: Kyung-Soo Jin, Jong-Jin Lim, Jong-Gil Byeon, Eun-Tae Kim, Jin-Ho Park
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Patent number: 8090069Abstract: The present invention relates to an apparatus for generating a clock signal with jitter and a test apparatus including the same. The apparatus for generating a clock signal with jitter in accordance with the present invention includes a voltage-controlled crystal oscillator (VCXO) for generating an output signal including jitter components based on a driving power source having a specific waveform and a controlled voltage, a phase comparator for calculating a phase difference of a reference signal and the output signal, and a loop filter for generating the controlled voltage based on the phase difference calculated by the phase comparator. Accordingly, the PLL circuit unit generates a clock signal including jitter, so that the complexity and manufacturing cost of the apparatus can be reduced.Type: GrantFiled: June 19, 2008Date of Patent: January 3, 2012Assignee: Electronics and Telecommunication Research InstituteInventors: Bong Guk Yu, Eun Tae Kim, Hyung Jung Kim, Gweon Do Jo
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Patent number: 7970021Abstract: Provided are a method and apparatus for derate matching a rate-matched data. The received data is deinterleaved and derate matched at a time, without using input buffers or constructing input buffers in parallel. Thus, a total process time necessary for the deinterleaving process and the derate matching process is reduced, and the use of memories such as the input buffers is minimized.Type: GrantFiled: August 20, 2009Date of Patent: June 28, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Eun Tae Kim, Dae Soon Cho, Hee Sang Chung, Hyeong Jun Park
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Publication number: 20100158053Abstract: Provided are a method and apparatus for derate matching a rate-matched data. The received data is deinterleaved and derate matched at a time, without using input buffers or constructing input buffers in parallel. Thus, a total process time necessary for the deinterleaving process and the derate matching process is reduced, and the use of memories such as the input buffers is minimized.Type: ApplicationFiled: August 20, 2009Publication date: June 24, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Eun Tae KIM, Dae Soon CHO, Hee Sang CHUNG, Hyeong Jun PARK
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Publication number: 20090316848Abstract: The present invention relates to an apparatus for generating a clock signal with jitter and a test apparatus including the same. The apparatus for generating a clock signal with jitter in accordance with the present invention includes a voltage-controlled crystal oscillator (VCXO) for generating an output signal including jitter components based on a driving power source having a specific waveform and a controlled voltage, a phase comparator for calculating a phase difference of a reference signal and the output signal, and a loop filter for generating the controlled voltage based on the phase difference calculated by the phase comparator. Accordingly, the PLL circuit unit generates a clock signal including jitter, so that the complexity and manufacturing cost of the apparatus can be reduced.Type: ApplicationFiled: June 19, 2008Publication date: December 24, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Bong Guk YU, Eun Tae Kim, Hyung Jung Kim, Gweon Do Jo