Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

Abstract: According to some embodiments of the present disclosure, a semiconductor device is provided. A gate electrode structure includes a plurality of first gate electrode layers separated by interlayer insulating layers on a substrate. A plurality of first channel structures extend through the gate electrode structure. An insulating layer is on the first channel structures and the gate electrode structure. A second gate electrode layer is on the insulating layer. A plurality of second channel structures extends through the second gate electrode layer. Each of the second channel structures is electrically coupled with one of the first channel structures, and each of the second channel structures includes a first portion extending through the second gate electrode layer and a second portion on the first portion. The first portion has a first width, and the second portion has a second width that is greater than the first width.

Abstract: A semiconductor device may include a peripheral circuit structure including cell region and an outside region, a cell structure on the cell region, an outside structure on the outside region, and an insulating layer. The outside structure may include a dummy stacked structure, a through electrode penetrating the dummy stacked structure and connected to the peripheral circuit structure, and a dummy vertical structure adjacent to the through electrode and penetrating at least a portion of the dummy stacked structure. The insulating layer may be between the dummy stacked structure and the peripheral circuit structure. The dummy stacked structure may include an upper dummy stacked structure on a lower dummy stacked structure. The upper dummy stacked structure may include upper dummy patterns stacked on the lower dummy stacked structure. The lower dummy stacked structure may include lower dummy patterns stacked on the outside region.

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure.

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.

Abstract: A vertical non-volatile memory device includes, a substrate, a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the substrate, the vertical direction being perpendicular to a surface of the substrate, a plurality of insulating layers between the gate lines, a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in a horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole, the horizontal direction being horizontal to the surface of the substrate, and a contact electrode at the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines.

Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device may include a stack structure extending in a first direction and including gate electrodes vertically stacked on a substrate, selection structures horizontally spaced apart on the stack structure, an upper isolation structure between the selection structure and extending in the first direction on the stack structure, and vertical structures penetrating the stack structure and the selection structures. The vertical structures include first vertical structures arranged along the first direction and penetrating portions of the upper isolation structure. Each selection structure includes a selection gate electrode and a horizontal dielectric pattern that surrounds top, bottom, and sidewall surfaces of the selection gate electrode.

Abstract: A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

Abstract: A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same are provided. A memory device may include a semiconductor layer including first and second regions, first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer, and second vertical structures on the second region and extending in the first direction. The first vertical structure may include a vertical semiconductor pattern extending in the first direction and in contact with the semiconductor layer, and a first data storage pattern surrounding the vertical semiconductor pattern. The second vertical structure may include an insulation structure extending in the first direction and in contact with the semiconductor layer, and a second data storage pattern surrounding the insulation structure.

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure.

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.