Patents by Inventor Eun Young JIN
Eun Young JIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11658853Abstract: An operation method of a receiver, which includes setting a coefficient of an equalizer based on one of a plurality of first codes, setting a coefficient of an amplifier based on one of a plurality of second codes, performing offset calibration by driving the equalizer and the amplifier based on the coefficient of the equalizer and the coefficient of the amplifier, storing an offset code corresponding to a voltage offset generated when the equalizer and the amplifier are driven, determining whether the offset calibration is completed, performing a normal operation of obtaining reception data from an input signal, in response to determining that the offset calibration is completed, and removing the voltage offset based on the offset code, in the normal operation.Type: GrantFiled: February 25, 2022Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Younghwan Chang, Eun-Young Jin, Youngseo Kim, Kilhoon Lee, Hyunwook Lim, Seng-Sub Chun
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Publication number: 20220376960Abstract: An operation method of a receiver, which includes setting a coefficient of an equalizer based on one of a plurality of first codes, setting a coefficient of an amplifier based on one of a plurality of second codes, performing offset calibration by driving the equalizer and the amplifier based on the coefficient of the equalizer and the coefficient of the amplifier, storing an offset code corresponding to a voltage offset generated when the equalizer and the amplifier are driven, determining whether the offset calibration is completed, performing a normal operation of obtaining reception data from an input signal, in response to determining that the offset calibration is completed, and removing the voltage offset based on the offset code, in the normal operation.Type: ApplicationFiled: February 25, 2022Publication date: November 24, 2022Inventors: YOUNGHWAN CHANG, EUN-YOUNG JIN, YOUNGSEO KIM, KILHOON LEE, HYUNWOOK LIM, SENG-SUB CHUN
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Patent number: 11450263Abstract: A method of operating a source driver, a display driving circuit, and a method of operating the display driving circuit are provided. The method of operating the source driver including a receiver, includes determining a parameter value of the receiver for optimizing a receiving of the receiver, through training, and transmitting the parameter value to a timing controller external to the source driver. The method of operating the source driver further includes, based on an abnormal state occurring in the receiving of the receiver, receiving the transmitted parameter value from the timing controller, and optimizing the receiving of the receiver based on the received parameter value.Type: GrantFiled: December 7, 2020Date of Patent: September 20, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-wook Lim, Kwi-sung Yoo, Young-min Choi, Jae-youl Lee, Dong-hoon Baek, Kyong-ho Kim, Eun-young Jin
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Patent number: 11277579Abstract: An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.Type: GrantFiled: November 8, 2019Date of Patent: March 15, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwi Sung Yoo, Eun Young Jin
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Publication number: 20210118356Abstract: A method of operating a source driver, a display driving circuit, and a method of operating the display driving circuit are provided. The method of operating the source driver including a receiver, includes determining a parameter value of the receiver for optimizing a receiving of the receiver, through training, and transmitting the parameter value to a timing controller external to the source driver. The method of operating the source driver further includes, based on an abnormal state occurring in the receiving of the receiver, receiving the transmitted parameter value from the timing controller, and optimizing the receiving of the receiver based on the received parameter value.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-wook Lim, Kwi-sung Yoo, Young-min Choi, Jae-youl Lee, Dong-hoon Baek, Kyong-ho Kim, Eun-young Jin
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Patent number: 10861375Abstract: A method of operating a source driver, a display driving circuit, and a method of operating the display driving circuit are provided. The method of operating the source driver including a receiver, includes determining a parameter value of the receiver for optimizing a receiving of the receiver, through training, and transmitting the parameter value to a timing controller external to the source driver. The method of operating the source driver further includes, based on an abnormal state occurring in the receiving of the receiver, receiving the transmitted parameter value from the timing controller, and optimizing the receiving of the receiver based on the received parameter value.Type: GrantFiled: September 12, 2016Date of Patent: December 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-wook Lim, Kwi-sung Yoo, Young-min Choi, Jae-youl Lee, Dong-hoon Baek, Kyong-ho Kim, Eun-young Jin
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Publication number: 20200077042Abstract: An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwi Sung Yoo, Eun Young Jin
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Patent number: 10506189Abstract: An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.Type: GrantFiled: June 2, 2015Date of Patent: December 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwi Sung Yoo, Eun Young Jin
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Patent number: 10170033Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.Type: GrantFiled: November 22, 2016Date of Patent: January 1, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwi Sung Yoo, Dong Hoon Baek, Dong Myung Lee, Hyun Wook Lim, Eun Young Jin, Jae Youl Lee
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Patent number: 10141963Abstract: A method of operating a receiver includes a controller of the receiver determining whether a full initialization or a partial initialization of the receiver is needed; the controller adjusting alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode, and the controller adjusting the DC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed.Type: GrantFiled: September 15, 2016Date of Patent: November 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwi-Sung Yoo, Jae-Youl Lee, Hyun-Wook Lim, Young-Min Choi, Dong-Hoon Baek, Kyong-Ho Kim, Eun-Young Jin
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Patent number: 9959835Abstract: A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.Type: GrantFiled: September 21, 2016Date of Patent: May 1, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hoon Baek, Hyunwook Lim, Kwi Sung Yoo, Eun-Young Jin, Kyongho Kim, JaeYoul Lee, Youngmin Choi
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Publication number: 20170148377Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.Type: ApplicationFiled: November 22, 2016Publication date: May 25, 2017Inventors: KWI SUNG YOO, Dong-Hoon Baek, Dong Myung Lee, Hyun Wook Lim, Eun Young Jin, Jae Youl Lee
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Publication number: 20170132966Abstract: A method of operating a source driver, a display driving circuit, and a method of operating the display driving circuit are provided. The method of operating the source driver including a receiver, includes determining a parameter value of the receiver for optimizing a receiving of the receiver, through training, and transmitting the parameter value to a timing controller external to the source driver. The method of operating the source driver further includes, based on an abnormal state occurring in the receiving of the receiver, receiving the transmitted parameter value from the timing controller, and optimizing the receiving of the receiver based on the received parameter value.Type: ApplicationFiled: September 12, 2016Publication date: May 11, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-wook LIM, Kwi-sung YOO, Young-min CHOI, Jae-youl LEE, Dong-hoon BAEK, Kyong-ho KIM, Eun-young JIN
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Publication number: 20170116954Abstract: A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.Type: ApplicationFiled: September 21, 2016Publication date: April 27, 2017Inventors: Dong-Hoon BAEK, Hyunwook LIM, Kwi Sung YOO, Eun-Young JIN, Kyongho KIM, JaeYoul LEE, Youngmin CHOI
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Publication number: 20170111071Abstract: A method of operating a receiver includes a controller of the receiver determining whether a full initialization or a partial initialization of the receiver is needed; the controller adjusting alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode, and the controller adjusting the DC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed.Type: ApplicationFiled: September 15, 2016Publication date: April 20, 2017Inventors: Kwi-Sung YOO, Jae-Youl LEE, Hyun-Wook LIM, Young-Min CHOI, Dong-Hoon BAEK, Kyong-Ho KIM, Eun-Young JIN
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Patent number: 9554073Abstract: An integrated circuit comprises a first signal transfer block comprising first through (M)-th aligning blocks that are cascade-coupled to produce first aligned control signals through (M)-th aligned control signals, respectively, by aligning first control signals with a clock signal, wherein M is an integer greater than one, and a functional block divided into first through (M)-th sub-functional blocks configured to perform a same function in parallel, each of the first through (M)-th sub-functional blocks operating according to corresponding ones of the first aligned control signals through (M)-th aligned control signals generated by the first through (M)-th aligning blocks.Type: GrantFiled: September 17, 2014Date of Patent: January 24, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Young Jin, Kyo-Jin Choo, Yu-Jin Park, Han-Kook Cho
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Patent number: 9521345Abstract: A data transmission circuit includes a data output unit (DOU) connected to a positive data transmission line and a negative data transmission line. The DOU generates a recovered data signal based on data signals communicated via the positive and negative data transmission lines. Data signal driving units are respectively connected at different points along the positive and negative data transmission lines, where each data signal driving unit generates and provides a positive data signal and a negative data signal based on a data input signal and a data transmission distance between the data signal driving unit and the data output unit.Type: GrantFiled: December 3, 2014Date of Patent: December 13, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Young Jin, Hyuk-Bin Kwon, Dae-Hwa Paik, Chang-Eun Kang, Won-Ho Choi, Young-Tae Jang, Ji-Hun Shin, Young-Kyun Jeong
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Patent number: 9509925Abstract: An image sensor is provided. The image sensor includes a converter configured to convert a photoelectric converted analog signal in a unit pixel into a digital signal including a plurality of bits, a data transfer unit configured to selectively output the converted digital signal output from the converter in units of bits in response to a control signal, and including a plurality of switching circuits which are serially connected; and a memory configured to store data output from the data transfer unit.Type: GrantFiled: January 5, 2015Date of Patent: November 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyojin David Choo, Eun-Young Jin, Seung-Hyun Lim
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Patent number: 9294703Abstract: A data transmission circuit of an image sensor includes first to Kth bus segments, and first to Kth data regeneration circuits respectively connected to the first to Kth bus segments and the first to (K?1)th data regeneration circuits respectively connected to the second to Kth bus segments. Each of the first to Kth data regeneration circuits may be embodied as one of a buffer, a logic gate, and a synchronous circuit operating in response to a clock signal.Type: GrantFiled: December 3, 2013Date of Patent: March 22, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyo Jin Choo, Eun Young Jin
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Publication number: 20150364518Abstract: An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.Type: ApplicationFiled: June 2, 2015Publication date: December 17, 2015Inventors: Kwi Sung Yoo, Eun Young Jin