Abstract: A semiconductor memory device is disclosed. The device comprises at least one data input/output reference signal input and output pin and a plurality of integrated circuits, each with a data input/output reference signal input and output pad connected to the data input/output reference signal input and output pin. Each integrated circuit further comprises a data input/output reference signal input and output buffer for buffering a data input/output reference signal input from the data input/output reference signal input and output pad when data is input. This buffer also buffers an internally generated data input/output reference signal, and outputs the buffered signal when data is output. The internally generated data input/output reference signal output can be disabled on each integrated circuit in response to a control signal, thus allowing a single one of the plurality of integrated circuits to be selected to generate the reference signal.

Abstract: Multi-chip memory devices include at least two integrated circuit memory chips, each of which includes corresponding address pads, data pads and control signal pads, and a common package that encapsulates the at least two integrated circuit memory chips, and that includes external terminals. An internal connection circuit in the common package is configured to connect at least one of the corresponding control signal pads of each of the integrated circuit memory chips to separate ones of the external terminals, to allow independent external control of each of the integrated circuit memory chips that are encapsulated in the common package. Multi-chip memory devices may be combined to form memory modules. The memory modules include a memory module substrate having first and second opposing surfaces. At least one multi-chip memory device, as described above, is provided on the first surface and on the second surface.

Abstract: A semiconductor memory device is disclosed. The device comprises at least one data input/output reference signal input and output pin and a plurality of integrated circuits, each with a data input/output reference signal input and output pad connected to the data input/output reference signal input and output pin. Each integrated circuit further comprises a data input/output reference signal input and output buffer for buffering a data input/output reference signal input from the data input/output reference signal input and output pad when data is input. This buffer also buffers an internally generated data input/output reference signal, and outputs the buffered signal when data is output. The internally generated data input/output reference signal output can be disabled on each integrated circuit in response to a control signal, thus allowing a single one of the plurality of integrated circuits to be selected to generate the reference signal.

Abstract: Multi-chip memory devices include at least two integrated circuit memory chips, each of which includes corresponding address pads, data pads and control signal pads, and a common package that encapsulates the at least two integrated circuit memory chips, and that includes external terminals. An internal connection circuit in the common package is configured to connect at least one of the corresponding control signal pads of each of the integrated circuit memory chips to separate ones of the external terminals, to allow independent external control of each of the integrated circuit memory chips that are encapsulated in the common package. Multi-chip memory devices may be combined to form memory modules. The memory modules include a memory module substrate having first and second opposing surfaces. At least one multi-chip memory device, as described above, is provided on the first surface and on the second surface.