Patents by Inventor Eung Bo Shim
Eung Bo Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973072Abstract: A display device includes: a base layer including a display area including an emission area and a non-emission area adjacent to the emission area, and a non-display area around the display area; a light emitting element in the emission area on the base layer; a color filter layer located above the light emitting element; and a light blocking pattern on the light emitting element and including a first light blocking pattern in the non-emission area and a second light blocking pattern in the non-display area. The first light blocking pattern and the second light blocking pattern are different in thickness from each other.Type: GrantFiled: June 24, 2021Date of Patent: April 30, 2024Assignee: Samsung Display Co., Ltd.Inventors: Eung Gyu Lee, Jin Suek Kim, Sae Ron Park, Seung Bo Shim, Ho Kil Oh, Jae Soo Jang
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Patent number: 11874734Abstract: A method for operating a memory includes: performing an error check operation on first memory cells; performing an error check operation on second memory cells; detecting an error which is equal to or greater than a threshold value in a region including the first memory cells and the second memory cells; classifying the region as a bad region in response to the detection of an error which is equal to or greater than the threshold value; and performing an error check operation on the first memory cells and the second memory cells again in response to the classification of the bad region.Type: GrantFiled: June 23, 2022Date of Patent: January 16, 2024Assignee: SK hynix Inc.Inventors: Dae Suk Kim, Eung Bo Shim
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Publication number: 20230289259Abstract: A method for operating a memory includes: performing an error check operation on first memory cells; performing an error check operation on second memory cells; detecting an error which is equal to or greater than a threshold value in a region including the first memory cells and the second memory cells; classifying the region as a bad region in response to the detection of an error which is equal to or greater than the threshold value; and performing an error check operation on the first memory cells and the second memory cells again in response to the classification of the bad region.Type: ApplicationFiled: June 23, 2022Publication date: September 14, 2023Inventors: Dae Suk KIM, Eung Bo SHIM
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Patent number: 11636014Abstract: A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.Type: GrantFiled: April 17, 2020Date of Patent: April 25, 2023Assignee: SK hynix Inc.Inventors: Eung-Bo Shim, Hyung-Sup Kim
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Patent number: 11609813Abstract: A data processing system comprising: a memory system comprising a plurality of memory devices, each of which comprises a first error correction unit and a plurality of cell array regions each having a plurality of memory cells coupled in an array to a plurality of word lines and a plurality of bit lines; and a host comprising a second error correction unit for correcting an error of data transferred from the memory system, and suitable for generating error correction information on the error correction operation of the second error correction unit, setting error correcting strengths to the respective memory devices using the error correction information and log information, and performing counter-error operations on the respective memory devices according to the error correcting strengths.Type: GrantFiled: July 8, 2020Date of Patent: March 21, 2023Assignee: SK hynix Inc.Inventors: Eung Bo Shim, Nam Young Ahn
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Publication number: 20230015404Abstract: A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.Type: ApplicationFiled: September 21, 2022Publication date: January 19, 2023Inventors: Eung-Bo SHIM, Hyung-Sup KIM
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Patent number: 11354069Abstract: An operating method of a data storage system comprising a processor and multiple storage devices, the operating method comprising: a first storage operation of selecting a first storage device, a second storage device, and a third storage device among the multiple storage devices and transmitting and storing data generated by the processor in the first storage device and the second storage device, a second storage operation of transmitting, to the third storage device, the data stored in the second storage device and compressing and storing the data in the third storage device, a first access operation of accessing the data in the first storage device, by the processor, after the first storage operation is completed, and a second access operation of accessing the data in the second storage device after fail of the first access operation.Type: GrantFiled: September 29, 2020Date of Patent: June 7, 2022Assignee: SK hynix Inc.Inventor: Eung Bo Shim
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Patent number: 11221931Abstract: A data processing system may include: a host; and a memory system including a plurality of memory units and a controller coupled to the plurality of memory units. The controller may include a memory manager suitable for acquiring characteristic data from serial presence detect (SPD) components in the plurality of memory units when power is supplied, providing the characteristic data to the host, setting an operation mode of each of the plurality of memory units based on the characteristic data, and performing memory training, and the host may perform interface training with the controller.Type: GrantFiled: November 5, 2019Date of Patent: January 11, 2022Assignee: SK hynix Inc.Inventor: Eung-Bo Shim
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Patent number: 11182231Abstract: A memory system suitable for counting the number of errors occurring in each memory location, and a host system suitable for detecting a defective memory location based on the number of the errors occurring in each memory location and controlling a repair operation for the defective memory location based on a current amount of data being processed between the host system and the memory system, wherein the memory system repairs the defective memory location using the redundant memory area.Type: GrantFiled: March 11, 2020Date of Patent: November 23, 2021Assignee: SK hynix Inc.Inventors: Eung-Bo Shim, Sung-Ki Choi
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Publication number: 20210326070Abstract: An operating method of a data storage system comprising a processor and multiple storage devices, the operating method comprising: a first storage operation of selecting a first storage device, a second storage device, and a third storage device among the multiple storage devices and transmitting and storing data generated by the processor in the first storage device and the second storage device, a second storage operation of transmitting, to the third storage device, the data stored in the second storage device and compressing and storing the data in the third storage device, a first access operation of accessing the data in the first storage device, by the processor, after the first storage operation is completed, and a second access operation of accessing the data in the second storage device after fail of the first access operation.Type: ApplicationFiled: September 29, 2020Publication date: October 21, 2021Inventor: Eung Bo SHIM
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Publication number: 20210271541Abstract: A data processing system includes a plurality of memory boards including a plurality of memory devices, and an error management controller that generates second error information based on plural pieces of first error information respectively received from each of the memory devices, and a memory error analysis device that analyzes the second error information received from the memory boards.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Inventor: Eung-Bo SHIM
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Publication number: 20210208966Abstract: A data processing system comprising: a memory system comprising a plurality of memory devices, each of which comprises a first error correction unit and a plurality of cell array regions each having a plurality of memory cells coupled in an array to a plurality of word lines and a plurality of bit lines; and a host comprising a second error correction unit for correcting an error of data transferred from the memory system, and suitable for generating error correction information on the error correction operation of the second error correction unit, setting error correcting strengths to the respective memory devices using the error correction information and log information, and performing counter-error operations on the respective memory devices according to the error correcting strengths.Type: ApplicationFiled: July 8, 2020Publication date: July 8, 2021Inventors: Eung Bo SHIM, Nam Young AHN
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Patent number: 11048573Abstract: A data processing system includes a plurality of memory boards including a plurality of memory devices, and an error management controller that generates second error information based on plural pieces of first error information respectively received from each of the memory devices, and a memory error analysis device that analyzes the second error information received from the memory boards.Type: GrantFiled: November 13, 2018Date of Patent: June 29, 2021Assignee: SK hynix Inc.Inventor: Eung-Bo Shim
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Publication number: 20210034446Abstract: A memory system suitable for counting the number of errors occurring in each memory location, and a host system suitable for detecting a defective memory location based on the number of the errors occurring in each memory location and controlling a repair operation for the defective memory location based on a current amount of data being processed between the host system and the memory system, wherein the memory system repairs the defective memory location using the redundant memory area.Type: ApplicationFiled: March 11, 2020Publication date: February 4, 2021Inventors: Eung-Bo SHIM, Sung-Ki CHOI
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Publication number: 20200241984Abstract: A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.Type: ApplicationFiled: April 17, 2020Publication date: July 30, 2020Inventors: Eung-Bo SHIM, Hyung-Sup KIM
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Publication number: 20200226044Abstract: A data processing system may include: a host; and a memory system including a plurality of memory units and a controller coupled to the plurality of memory units. The controller may include a memory manager suitable for acquiring characteristic data from serial presence detect (SPD) components in the plurality of memory units when power is supplied, providing the characteristic data to the host, setting an operation mode of each of the plurality of memory units based on the characteristic data, and performing memory training, and the host may perform interface training with the controller.Type: ApplicationFiled: November 5, 2019Publication date: July 16, 2020Inventor: Eung-Bo SHIM
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Patent number: 10558391Abstract: A data processing system includes: a memory device suitable for performing an operation corresponding to a command and outputting a memory data; a data collecting device suitable for collecting big data by integrating the command and the memory data at a predetermined cycle or at every predetermined time, splitting the collected big data based on a predetermined unit, and transferring the split big data; and a data processing device suitable for storing the split big data received from the data collecting device in block-based files in a High-Availability Distributed Object-Oriented Platform (HADOOP) distributed file system (HDFS), classifying the block-based files based on a particular memory command, and processing the block-based files.Type: GrantFiled: May 26, 2017Date of Patent: February 11, 2020Assignee: SK hynix Inc.Inventors: Kyu-Sun Lee, Nam-Young Ahn, Eung-Bo Shim
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Publication number: 20190220341Abstract: A data processing system includes a plurality of memory boards including a plurality of memory devices, and an error management controller that generates second error information based on plural pieces of first error information respectively received from each of the memory devices, and a memory error analysis device that analyzes the second error information received from the memory boards.Type: ApplicationFiled: November 13, 2018Publication date: July 18, 2019Inventor: Eung-Bo SHIM
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Patent number: 10325062Abstract: The present invention relates to a method and device for generating an engineering topology of a digital substation. The method may include: generating, by a single line diagram generation module, a single line diagram of the digital substation based on input information regarding a plurality of substation component devices and connection relations therebetween; converting, by a topology conversion module, the single line diagram of the digital substation into an engineering topology conforming to international standards by use of conversion conditions stored in a topology component management module; verifying, by a topology verification module, whether the engineering topology is suitable for the digital substation based on the international standards; and generating, by an international standard file generation module, a single line diagram engineering file of the digital substation as a system specification description (SSS) by use of the verified engineering topology.Type: GrantFiled: February 24, 2017Date of Patent: June 18, 2019Assignee: KOREA ELECTRIC POWER CORPORATIONInventors: Byung Tae Jang, Nam Ho Lee, Yong Ho An, Jong Kee Choi, Jeong Yeol Han, You Jin Lee, Eung Bo Shim, Dong Il Lee
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Patent number: 10169528Abstract: The present invention relates to a method and device for generating an engineering topology of a digital substation. The method may include: generating, by a single line diagram generation module, a single line diagram of the digital substation based on input information regarding a plurality of substation component devices and connection relations therebetween; converting, by a topology conversion module, the single line diagram of the digital substation into an engineering topology conforming to international standards by use of conversion conditions stored in a topology component management module; verifying, by a topology verification module, whether the engineering topology is suitable for the digital substation based on the international standards; and generating, by an international standard file generation module, a single line diagram engineering file of the digital substation as a system specification description (SSS) by use of the verified engineering topology.Type: GrantFiled: March 19, 2013Date of Patent: January 1, 2019Assignee: Korea Electric Power CorporationInventors: Byung Tae Jang, Nam Ho Lee, Yong Ho An, Jong Kee Choi, Jeong Yeol Han, You Jin Lee, Eung Bo Shim, Dong Il Lee