Patents by Inventor Eung-Joon Lee
Eung-Joon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230400673Abstract: The present invention relates to a flying-over beam pattern scanning hologram microscope device using a spatial modulation scanner and a translation stage. The present invention provides a flying-over beam pattern scanning hologram microscope device comprising: a scan beam generation unit which converts of a first beam and a second beam to a first spherical wave, and then makes the first and the second spherical waves interfere with each other to form a scan beam; a scanning unit, which comprises a spatial modulation scanner for controlling the scan beam in the horizontal direction, and a translation stage for moving an object in the vertical direction at the rear end of the projection unit; the projection unit projecting the scan beam onto an object plane; and a light collection unit which detects a beam that has passed through the objective lens again after being reflected or fluoresced from the object.Type: ApplicationFiled: March 7, 2022Publication date: December 14, 2023Applicant: CUBIXEL CO.,LTD.Inventors: Tae Geun KIM, Seung Ram LIM, Kyung Beom KIM, Eung Joon LEE, Dong Hwan IM
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FLYING-OVER BEAM PATTERN SCANNING HOLOGRAM MICROSCOPE DEVICE USING SCAN MIRROR AND TRANSLATION STAGE
Publication number: 20230324667Abstract: A flying-over beam pattern scanning hologram microscope device includes: a scan beam generation unit which converts a first beam and a second beam to a first spherical wave and a second spherical wave, and then allows the first and second spherical waves to interfere with each other to form a scan beam; a scanning unit, which comprises a scan mirror for controlling the scan beam in the horizontal direction, and a translation stage for moving an object in the vertical direction at the rear end of the projection unit; the projection unit projecting the scan beam onto an object plane; and a light collection unit for detecting a beam that has passed through the objective lens again after fluorescing or being reflected from an object.Type: ApplicationFiled: September 6, 2021Publication date: October 12, 2023Applicant: CUBIXEL CO.,LTD.Inventors: Tae Geun KIM, Tae Woong KIM, Seung Ram LIM, Kyung Beom KIM, Eung Joon LEE, Dong Hwan IM -
Publication number: 20210084717Abstract: Provided is a life jacket having a function of maintaining body temperature and preventing a drowning accident when water distress occurs. The life jacket includes: an inflatable buoyant member configured to be inflated to provide buoyancy; a jacket including a sealed bag, and being wearable on an upper body of a user; a vacuum pack having a spout and provided inside the sealed bag, the spout being configured such that an end thereof is exposed to an outside of the jacket; a self-triggering inflating body provided inside the vacuum pack; a heating element configured to generate heat by reacting with water flowing into the vacuum pack; and an interlock-type opening member, which is configured to open a stopper by being in conjunction with inflation of the inflatable buoyant member, the stopper being configured to normally close an inlet opening of the spout.Type: ApplicationFiled: November 18, 2019Publication date: March 18, 2021Inventor: Eung Joon LEE
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Patent number: 7566667Abstract: A semiconductor device is formed by forming a gate region, including a gate oxide layer, and impurity diffusion regions on a semiconductor substrate, forming a barrier metal layer on the gate region and the impurity diffusion regions of the semiconductor substrate, forming a passivation layer at an interface between the semiconductor substrate and the gate oxide layer to remove defects of the gate oxide layer, and then performing a nitridation process to remove impurities from the semiconductor substrate.Type: GrantFiled: November 22, 2005Date of Patent: July 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eung-Joon Lee, Hyun-Young Kim, In-Sun Park, Hyun-Deok Lee
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Patent number: 7375025Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.Type: GrantFiled: November 16, 2005Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Eung-Joon Lee, In-Sun Park, Kwan-Jong Roh
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Patent number: 7311109Abstract: A method for cleaning a processing chamber and manufacturing a semiconductor device by removing impurities from a substrate in the processing chamber with a plasma of a first gas including hydrogen gas. After the substrate is removed from the processing chamber, the processing chamber is etched with the plasma of a non-hydrogenous second gas. Thus, the etching selectivity can be improved and the particles are prevented from depositing and/or forming on the substrate.Type: GrantFiled: June 26, 2003Date of Patent: December 25, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-wook Kim, Hyeon-Deok Lee, Jin-Gi Hong, Ji-Soon Park, Eung-Joon Lee
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Patent number: 7199019Abstract: A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.Type: GrantFiled: December 3, 2004Date of Patent: April 3, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Soon Park, Hyun-Seok Lim, Eung-Joon Lee, Jung-Wook Kim
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Publication number: 20060113615Abstract: A semiconductor device is formed by forming a gate region, including a gate oxide layer, and impurity diffusion regions on a semiconductor substrate, forming a barrier metal layer on the gate region and the impurity diffusion regions of the semiconductor substrate, forming a passivation layer at an interface between the semiconductor substrate and the gate oxide layer to remove defects of the gate oxide layer, and then performing a nitridation process to remove impurities from the semiconductor substrate.Type: ApplicationFiled: November 22, 2005Publication date: June 1, 2006Inventors: Eung-Joon Lee, Hyun-Young Kim, In-Sun Park, Hyun-Deok Lee
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Publication number: 20060068585Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.Type: ApplicationFiled: November 16, 2005Publication date: March 30, 2006Inventors: Eung-Joon Lee, In-Sun Park, Kwan-Jong Roh
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Patent number: 7005373Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.Type: GrantFiled: March 2, 2004Date of Patent: February 28, 2006Assignee: Samsung Electronics, Co., Ltd.Inventors: Eung-Joon Lee, In-Sun Park, Kwan-Jong Roh
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Publication number: 20050146045Abstract: A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.Type: ApplicationFiled: December 3, 2004Publication date: July 7, 2005Inventors: Ji-Soon Park, Hyun-Seok Lim, Eung-Joon Lee, Jung-Wook Kim
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Patent number: 6797618Abstract: A conductive pattern having a surface including silicon is formed on a substrate of a semiconductor device and a conduction region having a surface including silicon is formed in the substrate. A radio frequency etching process is performed ex-situ to remove impurities from a resultant structure and to improve surface characteristics of the conduction region. Residues generated during the radio frequency etching process are removed from the conductive pattern and the conduction region by a cleaning process. A metal film is formed on the conductive pattern and the conduction region. A silicide film is formed on the conductive pattern and the conduction region by reacting metal of the metal film and silicon in the conductive pattern and the conduction region. With a radio frequency sputtering process and a wet cleaning process, a metal silicide film having a uniform phase may be stably formed.Type: GrantFiled: July 29, 2003Date of Patent: September 28, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Eung-Joon Lee, In-Sun Park, Ji-Soon Park
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Publication number: 20040175890Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.Type: ApplicationFiled: March 2, 2004Publication date: September 9, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Eung-Joon Lee, In-Sun Park, Kwan-Jong Roh
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Publication number: 20040074515Abstract: A method for cleaning a processing chamber and manufacturing a semiconductor device by removing impurities from a substrate in the processing chamber with a plasma of a first gas including hydrogen gas. After the substrate is removed from the processing chamber, the processing chamber is etched with the plasma of a non-hydrogenous second gas. Thus, the etching selectivity can be improved and the particles are prevented from depositing and/or forming on the substrate.Type: ApplicationFiled: June 26, 2003Publication date: April 22, 2004Inventors: Jung-Wook Kim, Hyeon-Deok Lee, Jin-Gi Hong, Ji-Soon Park, Eung-Joon Lee
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Publication number: 20040058500Abstract: A conductive pattern having a surface including silicon is formed on a substrate of a semiconductor device and a conduction region having a surface including silicon is formed in the substrate. A radio frequency etching process is performed ex-situ to remove impurities from a resultant structure and to improve surface characteristics of the conduction region. Residues generated during the radio frequency etching process are removed from the conductive pattern and the conduction region by a cleaning process. A metal film is formed on the conductive pattern and the conduction region. A silicide film is formed on the conductive pattern and the conduction region by reacting metal of the metal film and silicon in the conductive pattern and the conduction region. With a radio frequency sputtering process and a wet cleaning process, a metal silicide film having a uniform phase may be stably formed.Type: ApplicationFiled: July 29, 2003Publication date: March 25, 2004Inventors: Eung-Joon Lee, In-Sun Park, Ji-Soon Park
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Patent number: 6355554Abstract: Methods of fabricating an interconnection to an underlying microelectronic layer include removing a portion of the insulation layer to form a plurality of contact holes having different contact sizes therethrough and thereby expose a portion of the microelectronic layer. A conductive material is deposited on the insulation layer and in the contact hole with a sufficient thickness such that a bridge is generated in the largest contact hole. The deposited conductive material is then reflowed to fill the contact hole and form an interconnection to the underlying microelectronic layer, by supplying a high pressure such that at least the void formed in the largest contact hole is filled. The conductive material may be planarized to thereby expose the insulation layer. The present invention may be applied to an asymmetrical contact hole, for example, a dual damascene structure.Type: GrantFiled: January 13, 2000Date of Patent: March 12, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Gil-heyun Choi, Eung-joon Lee, Byeong-jun Kim
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Patent number: 6329276Abstract: There is provided a semiconductor device fabrication method. In the method, a gate layer is formed on a semiconductor substrate and patterned to form a first resultant structure, a metal layer is formed on the first resultant structure, a capping layer is formed on the metal layer, a metal silicide is formed on the gate layer by heating the substrate at a first temperature, unreacted metal layer and first capping layer are removed to form a second resultant structure, a second capping layer is formed on the second resultant structure, and the substrate is heated at a second temperature higher than the first temperature. The second capping layer suppresses a silicidation rate in the secondary heat treatment, thereby allowing a silicide of a good morphology to be achieved.Type: GrantFiled: September 9, 1999Date of Patent: December 11, 2001Assignee: Samsung Electronics Co. Ltd.Inventors: Ja-Hum Ku, Soo-Geun Lee, Chul-Sung Kim, Tae-Wook Seo, Eung-Joon Lee, Joo-Hyuk Chung